442 lines
12 KiB
C
442 lines
12 KiB
C
/*
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* Copyright (c) 2017 - 2018, Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <drivers/counter.h>
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#include <hal/nrf_timer.h>
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#include <sys/atomic.h>
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#define LOG_LEVEL CONFIG_COUNTER_LOG_LEVEL
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#define LOG_MODULE_NAME counter_timer
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#include <logging/log.h>
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LOG_MODULE_REGISTER(LOG_MODULE_NAME, LOG_LEVEL);
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#define TIMER_CLOCK 16000000
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#define CC_TO_ID(cc_num) (cc_num - 2)
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#define ID_TO_CC(idx) (nrf_timer_cc_channel_t)(idx + 2)
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#define TOP_CH NRF_TIMER_CC_CHANNEL0
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#define COUNTER_TOP_EVT NRF_TIMER_EVENT_COMPARE0
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#define COUNTER_TOP_INT_MASK NRF_TIMER_INT_COMPARE0_MASK
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#define COUNTER_OVERFLOW_SHORT NRF_TIMER_SHORT_COMPARE0_CLEAR_MASK
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#define COUNTER_READ_CC NRF_TIMER_CC_CHANNEL1
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struct counter_nrfx_data {
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counter_top_callback_t top_cb;
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void *top_user_data;
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u32_t guard_period;
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atomic_t cc_int_pending;
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};
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struct counter_nrfx_ch_data {
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counter_alarm_callback_t callback;
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void *user_data;
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};
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struct counter_nrfx_config {
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struct counter_config_info info;
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struct counter_nrfx_ch_data *ch_data;
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NRF_TIMER_Type *timer;
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LOG_INSTANCE_PTR_DECLARE(log);
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};
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struct counter_timer_config {
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nrf_timer_bit_width_t bit_width;
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nrf_timer_mode_t mode;
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nrf_timer_frequency_t freq;
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};
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static inline struct counter_nrfx_data *get_dev_data(struct device *dev)
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{
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return dev->driver_data;
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}
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static inline const struct counter_nrfx_config *get_nrfx_config(
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struct device *dev)
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{
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return CONTAINER_OF(dev->config->config_info,
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struct counter_nrfx_config, info);
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}
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static int start(struct device *dev)
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{
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nrf_timer_task_trigger(get_nrfx_config(dev)->timer,
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NRF_TIMER_TASK_START);
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return 0;
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}
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static int stop(struct device *dev)
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{
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nrf_timer_task_trigger(get_nrfx_config(dev)->timer,
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NRF_TIMER_TASK_SHUTDOWN);
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return 0;
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}
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static u32_t get_top_value(struct device *dev)
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{
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return nrf_timer_cc_read(get_nrfx_config(dev)->timer, TOP_CH);
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}
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static u32_t get_max_relative_alarm(struct device *dev)
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{
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return get_top_value(dev);
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}
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static u32_t read(struct device *dev)
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{
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NRF_TIMER_Type *timer = get_nrfx_config(dev)->timer;
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nrf_timer_task_trigger(timer,
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nrf_timer_capture_task_get(COUNTER_READ_CC));
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return nrf_timer_cc_read(timer, COUNTER_READ_CC);
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}
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/* Return true if value equals 2^n - 1 */
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static inline bool is_bit_mask(u32_t val)
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{
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return !(val & (val + 1));
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}
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static u32_t ticks_add(u32_t val1, u32_t val2, u32_t top)
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{
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u32_t to_top;
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if (likely(is_bit_mask(top))) {
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return (val1 + val2) & top;
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}
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to_top = top - val1;
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return (val2 <= to_top) ? val1 + val2 : val2 - to_top;
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}
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static u32_t ticks_sub(u32_t val, u32_t old, u32_t top)
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{
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if (likely(is_bit_mask(top))) {
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return (val - old) & top;
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}
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/* if top is not 2^n-1 */
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return (val >= old) ? (val - old) : val + top + 1 - old;
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}
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static void set_cc_int_pending(struct device *dev, u8_t chan)
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{
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atomic_or(&get_dev_data(dev)->cc_int_pending, BIT(chan));
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NRFX_IRQ_PENDING_SET(NRFX_IRQ_NUMBER_GET(get_nrfx_config(dev)->timer));
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}
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static int set_cc(struct device *dev, u8_t id, u32_t val, u32_t flags)
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{
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__ASSERT_NO_MSG(get_dev_data(dev)->guard_period < get_top_value(dev));
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bool absolute = flags & COUNTER_ALARM_CFG_ABSOLUTE;
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bool irq_on_late;
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NRF_TIMER_Type *reg = get_nrfx_config(dev)->timer;
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u8_t chan = ID_TO_CC(id);
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nrf_timer_event_t evt = nrf_timer_compare_event_get(chan);
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u32_t top = get_top_value(dev);
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int err = 0;
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u32_t prev_val;
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u32_t now;
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u32_t diff;
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u32_t max_rel_val;
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__ASSERT(nrf_timer_int_enable_check(reg,
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nrf_timer_compare_int_get(chan)) == 0,
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"Expected that CC interrupt is disabled.");
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/* First take care of a risk of an event coming from CC being set to
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* next tick. Reconfigure CC to future (now tick is the furtherest
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* future).
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*/
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now = read(dev);
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prev_val = nrf_timer_cc_read(reg, chan);
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nrf_timer_cc_write(reg, chan, now);
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nrf_timer_event_clear(reg, evt);
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if (absolute) {
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max_rel_val = top - get_dev_data(dev)->guard_period;
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irq_on_late = flags & COUNTER_ALARM_CFG_EXPIRE_WHEN_LATE;
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} else {
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/* If relative value is smaller than half of the counter range
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* it is assumed that there is a risk of setting value too late
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* and late detection algorithm must be applied. When late
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* setting is detected, interrupt shall be triggered for
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* immediate expiration of the timer. Detection is performed
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* by limiting relative distance between CC and counter.
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*
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* Note that half of counter range is an arbitrary value.
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*/
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irq_on_late = val < (top / 2);
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/* limit max to detect short relative being set too late. */
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max_rel_val = irq_on_late ? top / 2 : top;
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val = ticks_add(now, val, top);
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}
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nrf_timer_cc_write(reg, chan, val);
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/* decrement value to detect also case when val == read(dev). Otherwise,
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* condition would need to include comparing diff against 0.
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*/
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diff = ticks_sub(val - 1, read(dev), top);
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if (diff > max_rel_val) {
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if (absolute) {
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err = -ETIME;
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}
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/* Interrupt is triggered always for relative alarm and
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* for absolute depending on the flag.
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*/
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if (irq_on_late) {
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set_cc_int_pending(dev, chan);
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} else {
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get_nrfx_config(dev)->ch_data[id].callback = NULL;
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}
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} else {
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nrf_timer_int_enable(reg, nrf_timer_compare_int_get(chan));
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}
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return err;
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}
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static int set_alarm(struct device *dev, u8_t chan,
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const struct counter_alarm_cfg *alarm_cfg)
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{
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const struct counter_nrfx_config *nrfx_config = get_nrfx_config(dev);
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struct counter_nrfx_ch_data *chdata = &nrfx_config->ch_data[chan];
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if (alarm_cfg->ticks > get_top_value(dev)) {
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return -EINVAL;
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}
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if (chdata->callback) {
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return -EBUSY;
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}
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chdata->callback = alarm_cfg->callback;
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chdata->user_data = alarm_cfg->user_data;
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return set_cc(dev, chan, alarm_cfg->ticks, alarm_cfg->flags);
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}
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static int cancel_alarm(struct device *dev, u8_t chan_id)
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{
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const struct counter_nrfx_config *config = get_nrfx_config(dev);
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u32_t int_mask = nrf_timer_compare_int_get(ID_TO_CC(chan_id));
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nrf_timer_int_disable(config->timer, int_mask);
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config->ch_data[chan_id].callback = NULL;
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return 0;
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}
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static int set_top_value(struct device *dev, const struct counter_top_cfg *cfg)
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{
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const struct counter_nrfx_config *nrfx_config = get_nrfx_config(dev);
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NRF_TIMER_Type *timer = get_nrfx_config(dev)->timer;
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struct counter_nrfx_data *data = get_dev_data(dev);
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int err = 0;
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for (int i = 0; i < counter_get_num_of_channels(dev); i++) {
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/* Overflow can be changed only when all alarms are
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* disables.
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*/
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if (nrfx_config->ch_data[i].callback) {
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return -EBUSY;
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}
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}
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nrf_timer_int_disable(timer, COUNTER_TOP_INT_MASK);
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nrf_timer_cc_write(timer, TOP_CH, cfg->ticks);
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nrf_timer_shorts_enable(timer, COUNTER_OVERFLOW_SHORT);
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data->top_cb = cfg->callback;
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data->top_user_data = cfg->user_data;
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if (!(cfg->flags & COUNTER_TOP_CFG_DONT_RESET)) {
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nrf_timer_task_trigger(timer, NRF_TIMER_TASK_CLEAR);
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} else if (read(dev) >= cfg->ticks) {
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err = -ETIME;
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if (cfg->flags & COUNTER_TOP_CFG_RESET_WHEN_LATE) {
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nrf_timer_task_trigger(timer, NRF_TIMER_TASK_CLEAR);
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}
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}
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if (cfg->callback) {
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nrf_timer_int_enable(timer, COUNTER_TOP_INT_MASK);
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}
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return err;
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}
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static u32_t get_pending_int(struct device *dev)
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{
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return 0;
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}
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static int init_timer(struct device *dev,
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const struct counter_timer_config *config)
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{
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NRF_TIMER_Type *reg = get_nrfx_config(dev)->timer;
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nrf_timer_bit_width_set(reg, config->bit_width);
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nrf_timer_mode_set(reg, config->mode);
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nrf_timer_frequency_set(reg, config->freq);
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nrf_timer_cc_write(reg, TOP_CH, counter_get_max_top_value(dev));
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NRFX_IRQ_ENABLE(NRFX_IRQ_NUMBER_GET(reg));
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return 0;
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}
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static u32_t get_guard_period(struct device *dev, u32_t flags)
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{
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return get_dev_data(dev)->guard_period;
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}
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static int set_guard_period(struct device *dev, u32_t guard, u32_t flags)
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{
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__ASSERT_NO_MSG(guard < get_top_value(dev));
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get_dev_data(dev)->guard_period = guard;
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return 0;
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}
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static void top_irq_handle(struct device *dev)
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{
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NRF_TIMER_Type *reg = get_nrfx_config(dev)->timer;
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counter_top_callback_t cb = get_dev_data(dev)->top_cb;
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if (nrf_timer_event_check(reg, COUNTER_TOP_EVT) &&
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nrf_timer_int_enable_check(reg, COUNTER_TOP_INT_MASK)) {
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nrf_timer_event_clear(reg, COUNTER_TOP_EVT);
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__ASSERT(cb != NULL, "top event enabled - expecting callback");
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cb(dev, get_dev_data(dev)->top_user_data);
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}
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}
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static void alarm_irq_handle(struct device *dev, u32_t id)
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{
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u32_t cc = ID_TO_CC(id);
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NRF_TIMER_Type *reg = get_nrfx_config(dev)->timer;
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u32_t int_mask = nrf_timer_compare_int_get(cc);
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nrf_timer_event_t evt = nrf_timer_compare_event_get(cc);
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bool hw_irq_pending = nrf_timer_event_check(reg, evt) &&
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nrf_timer_int_enable_check(reg, int_mask);
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bool sw_irq_pending = get_dev_data(dev)->cc_int_pending & BIT(cc);
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if (hw_irq_pending || sw_irq_pending) {
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struct counter_nrfx_ch_data *chdata;
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counter_alarm_callback_t cb;
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nrf_timer_event_clear(reg, evt);
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atomic_and(&get_dev_data(dev)->cc_int_pending, ~BIT(cc));
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nrf_timer_int_disable(reg, int_mask);
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chdata = &get_nrfx_config(dev)->ch_data[id];
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cb = chdata->callback;
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chdata->callback = NULL;
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if (cb) {
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u32_t cc_val = nrf_timer_cc_read(reg, cc);
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cb(dev, id, cc_val, chdata->user_data);
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}
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}
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}
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static void irq_handler(struct device *dev)
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{
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top_irq_handle(dev);
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for (u32_t i = 0; i < counter_get_num_of_channels(dev); i++) {
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alarm_irq_handle(dev, i);
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}
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}
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static const struct counter_driver_api counter_nrfx_driver_api = {
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.start = start,
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.stop = stop,
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.read = read,
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.set_alarm = set_alarm,
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.cancel_alarm = cancel_alarm,
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.set_top_value = set_top_value,
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.get_pending_int = get_pending_int,
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.get_top_value = get_top_value,
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.get_max_relative_alarm = get_max_relative_alarm,
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.get_guard_period = get_guard_period,
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.set_guard_period = set_guard_period,
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};
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#define COUNTER_NRFX_TIMER_DEVICE(idx) \
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BUILD_ASSERT_MSG(DT_NORDIC_NRF_TIMER_TIMER_##idx##_PRESCALER <= \
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TIMER_PRESCALER_PRESCALER_Msk, \
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"TIMER prescaler out of range"); \
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DEVICE_DECLARE(timer_##idx); \
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static int counter_##idx##_init(struct device *dev) \
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{ \
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IRQ_CONNECT(DT_NORDIC_NRF_TIMER_TIMER_##idx##_IRQ_0, \
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DT_NORDIC_NRF_TIMER_TIMER_##idx##_IRQ_0_PRIORITY, \
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irq_handler, DEVICE_GET(timer_##idx), 0); \
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static const struct counter_timer_config config = { \
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.freq = DT_NORDIC_NRF_TIMER_TIMER_##idx##_PRESCALER, \
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.mode = NRF_TIMER_MODE_TIMER, \
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.bit_width = (TIMER##idx##_MAX_SIZE == 32) ? \
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NRF_TIMER_BIT_WIDTH_32 : \
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NRF_TIMER_BIT_WIDTH_16, \
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}; \
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return init_timer(dev, &config); \
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} \
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static struct counter_nrfx_data counter_##idx##_data; \
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static struct counter_nrfx_ch_data \
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counter##idx##_ch_data[CC_TO_ID(TIMER##idx##_CC_NUM)]; \
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LOG_INSTANCE_REGISTER(LOG_MODULE_NAME, idx, CONFIG_COUNTER_LOG_LEVEL); \
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static const struct counter_nrfx_config nrfx_counter_##idx##_config = {\
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.info = { \
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.max_top_value = (TIMER##idx##_MAX_SIZE == 32) ? \
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0xffffffff : 0x0000ffff, \
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.freq = TIMER_CLOCK / \
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(1 << DT_NORDIC_NRF_TIMER_TIMER_##idx##_PRESCALER), \
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.flags = COUNTER_CONFIG_INFO_COUNT_UP, \
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.channels = CC_TO_ID(TIMER##idx##_CC_NUM), \
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}, \
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.ch_data = counter##idx##_ch_data, \
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.timer = NRF_TIMER##idx, \
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LOG_INSTANCE_PTR_INIT(log, LOG_MODULE_NAME, idx) \
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}; \
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DEVICE_AND_API_INIT(timer_##idx, \
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DT_NORDIC_NRF_TIMER_TIMER_##idx##_LABEL, \
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counter_##idx##_init, \
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&counter_##idx##_data, \
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&nrfx_counter_##idx##_config.info, \
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
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&counter_nrfx_driver_api)
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#ifdef CONFIG_COUNTER_TIMER0
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COUNTER_NRFX_TIMER_DEVICE(0);
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#endif
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#ifdef CONFIG_COUNTER_TIMER1
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COUNTER_NRFX_TIMER_DEVICE(1);
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#endif
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#ifdef CONFIG_COUNTER_TIMER2
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COUNTER_NRFX_TIMER_DEVICE(2);
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#endif
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#ifdef CONFIG_COUNTER_TIMER3
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COUNTER_NRFX_TIMER_DEVICE(3);
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#endif
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#ifdef CONFIG_COUNTER_TIMER4
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COUNTER_NRFX_TIMER_DEVICE(4);
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#endif
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