159fa4888b
Sometimes, channel C may write wrong register to the target device. This issue occurs when FIFO2 is enabled on channel C. The problem arises because FIFO2 is shared between channel B and channel C. FIFO2 will be disabled when data access is completed, at which point FIFO2 is set to the default configuration for channel B. The byte counter of FIFO2 may be affected by channel B. There is a chance that channel C may encounter wrong register being written due to the FIFO2 byte counter wrong write after channel B's write operation. The current workaround is that channel C cannot use FIFO mode. Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com> |
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| .. | ||
| andes | ||
| efinix | ||
| espressif/esp32c3 | ||
| gigadevice | ||
| ite | ||
| lowrisc | ||
| microchip | ||
| niosv | ||
| openisa | ||
| sifive | ||
| starfive | ||
| telink | ||
| neorv32.dtsi | ||
| riscv32-litex-vexriscv.dtsi | ||
| virt.dtsi | ||