122 lines
4.3 KiB
C
122 lines
4.3 KiB
C
/*
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* Copyright (c) 2023 Andes Technology Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* Flash opcodes */
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#define FLASH_ANDES_CMD_WRSR 0x01 /* Write status register */
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#define FLASH_ANDES_CMD_RDSR 0x05 /* Read status register */
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#define FLASH_ANDES_CMD_READ 0x03 /* Read data */
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#define FLASH_ANDES_CMD_4READ 0xEB /* Quad mode Read data*/
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#define FLASH_ANDES_CMD_WREN 0x06 /* Write enable */
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#define FLASH_ANDES_CMD_WRDI 0x04 /* Write disable */
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#define FLASH_ANDES_CMD_PP 0x02 /* Page program */
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#define FLASH_ANDES_CMD_4PP 0x38 /* Quad mode page program*/
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#define FLASH_ANDES_CMD_SE 0x20 /* Sector erase */
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#define FLASH_ANDES_CMD_BE_32K 0x52 /* Block erase 32KB */
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#define FLASH_ANDES_CMD_BE 0xD8 /* Block erase */
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#define FLASH_ANDES_CMD_CE 0xC7 /* Chip erase */
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#define FLASH_ANDES_CMD_RDID 0x9F /* Read JEDEC ID */
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#define FLASH_ANDES_CMD_ULBPR 0x98 /* Global Block Protection Unlock */
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#define FLASH_ANDES_CMD_DPD 0xB9 /* Deep Power Down */
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#define FLASH_ANDES_CMD_RDPD 0xAB /* Release from Deep Power Down */
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/* Status register bits */
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#define FLASH_ANDES_WIP_BIT BIT(0) /* Write in progress */
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#define FLASH_ANDES_WEL_BIT BIT(1) /* Write enable latch */
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#define FLASH_ANDES_QE_BIT BIT(6)
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#define QSPI_TFMAT(base) (base + 0x10)
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#define QSPI_TCTRL(base) (base + 0x20)
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#define QSPI_CMD(base) (base + 0x24)
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#define QSPI_ADDR(base) (base + 0x28)
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#define QSPI_DATA(base) (base + 0x2c)
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#define QSPI_CTRL(base) (base + 0x30)
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#define QSPI_STAT(base) (base + 0x34)
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#define QSPI_INTEN(base) (base + 0x38)
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#define QSPI_INTST(base) (base + 0x3c)
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#define QSPI_TIMIN(base) (base + 0x40)
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#define QSPI_CONFIG(base) (base + 0x7c)
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/* Field mask of SPI transfer format register */
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#define TFMAT_DATA_LEN_OFFSET (8)
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#define TFMAT_ADDR_LEN_OFFSET (16)
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#define TFMAT_SLVMODE_MSK BIT(2)
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#define TFMAT_DATA_MERGE_MSK BIT(7)
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#define TFMAT_DATA_LEN_MSK GENMASK(12, 8)
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/* Field mask of SPI transfer control register */
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#define TCTRL_RD_TCNT_OFFSET (0)
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#define TCTRL_DUMMY_CNT_OFFSET (9)
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#define TCTRL_WR_TCNT_OFFSET (12)
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#define TCTRL_DUAL_MODE_OFFSET (22)
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#define TCTRL_TRNS_MODE_OFFSET (24)
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#define TCTRL_TRNS_MODE_MSK GENMASK(27, 24)
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#define TCTRL_ADDR_FMT_MSK BIT(28)
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#define TCTRL_ADDR_EN_MSK BIT(29)
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#define TCTRL_CMD_EN_MSK BIT(30)
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/* Transfer mode */
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#define TRNS_MODE_WRITE_READ (0 << TCTRL_TRNS_MODE_OFFSET)
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#define TRNS_MODE_WRITE_ONLY (1 << TCTRL_TRNS_MODE_OFFSET)
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#define TRNS_MODE_READ_ONLY (2 << TCTRL_TRNS_MODE_OFFSET)
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#define TRNS_MODE_NONE_DATA (7 << TCTRL_TRNS_MODE_OFFSET)
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#define TRNS_MODE_DUMMY_READ (9 << TCTRL_TRNS_MODE_OFFSET)
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/* Dual/Qual mode */
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#define DUAL_IO_MODE (2 << TCTRL_DUAL_MODE_OFFSET)
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/* Dummy count */
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/* In Qual mode, dummy count 3 implies 6 dummy cycles */
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#define DUMMY_CNT_3 (0x2 << TCTRL_DUMMY_CNT_OFFSET)
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/* Field mask of SPI interrupt enable register */
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#define IEN_RX_FIFO_MSK BIT(2)
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#define IEN_TX_FIFO_MSK BIT(3)
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#define IEN_END_MSK BIT(4)
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/* Field mask of SPI interrupt status register */
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#define INTST_RX_FIFO_INT_MSK BIT(2)
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#define INTST_TX_FIFO_INT_MSK BIT(3)
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#define INTST_END_INT_MSK BIT(4)
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/* Field mask of SPI config register */
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#define CFG_RX_FIFO_SIZE_MSK GENMASK(3, 0)
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#define CFG_TX_FIFO_SIZE_MSK GENMASK(7, 4)
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/* Field mask of SPI status register */
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#define STAT_RX_NUM_MSK GENMASK(13, 8)
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#define STAT_TX_NUM_MSK GENMASK(21, 16)
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/* Field mask of SPI control register */
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#define CTRL_RX_THRES_OFFSET (8)
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#define CTRL_TX_THRES_OFFSET (16)
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#define CTRL_RX_THRES_MSK GENMASK(15, 8)
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#define CTRL_TX_THRES_MSK GENMASK(23, 16)
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/* Field mask of SPI status register */
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#define TIMIN_SCLK_DIV_MSK GENMASK(7, 0)
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#define TX_FIFO_THRESHOLD (1 << CTRL_TX_THRES_OFFSET)
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#define RX_FIFO_THRESHOLD (1 << CTRL_RX_THRES_OFFSET)
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#define MAX_TRANSFER_CNT (512)
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#define TX_FIFO_SIZE_SETTING(base) \
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(sys_read32(QSPI_CONFIG(base)) & CFG_TX_FIFO_SIZE_MSK)
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#define TX_FIFO_SIZE(base) \
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(2 << (TX_FIFO_SIZE_SETTING(base) >> 4))
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#define RX_FIFO_SIZE_SETTING(base) \
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(sys_read32(QSPI_CONFIG(base)) & CFG_RX_FIFO_SIZE_MSK)
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#define RX_FIFO_SIZE(base) \
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(2 << (RX_FIFO_SIZE_SETTING(base) >> 0))
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#define TX_NUM_STAT(base) (sys_read32(QSPI_STAT(base)) & STAT_TX_NUM_MSK)
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#define RX_NUM_STAT(base) (sys_read32(QSPI_STAT(base)) & STAT_RX_NUM_MSK)
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#define GET_TX_NUM(base) (TX_NUM_STAT(base) >> 16)
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#define GET_RX_NUM(base) (RX_NUM_STAT(base) >> 8)
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