553 lines
14 KiB
C
553 lines
14 KiB
C
/*
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* Copyright (c) 2019 Mohamed ElShahawi (extremegtx@hotmail.com)
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT espressif_esp32_uart
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/* Include esp-idf headers first to avoid redefining BIT() macro */
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#include <rom/ets_sys.h>
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#include <soc/dport_reg.h>
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#include <rom/gpio.h>
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#include <soc/gpio_sig_map.h>
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#include <device.h>
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#include <soc.h>
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#include <drivers/uart.h>
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#include <errno.h>
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#include <sys/util.h>
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/*
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* ESP32 UARTx register map structure
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*/
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struct uart_esp32_regs_t {
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u32_t fifo;
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u32_t int_raw;
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u32_t int_st;
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u32_t int_ena;
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u32_t int_clr;
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u32_t clk_div;
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u32_t auto_baud;
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u32_t status;
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u32_t conf0;
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u32_t conf1;
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u32_t lowpulse;
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u32_t highpulse;
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u32_t rxd_cnt;
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u32_t flow_conf;
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u32_t sleep_conf;
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u32_t swfc_conf;
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u32_t idle_conf;
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u32_t rs485_conf;
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u32_t at_cmd_precnt;
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u32_t at_cmd_postcnt;
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u32_t at_cmd_gaptout;
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u32_t at_cmd_char;
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u32_t mem_conf;
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u32_t mem_tx_status;
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u32_t mem_rx_status;
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u32_t mem_cnt_status;
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u32_t pospulse;
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u32_t negpulse;
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u32_t reserved_0;
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u32_t reserved_1;
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u32_t date;
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u32_t id;
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};
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struct uart_esp32_config {
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struct uart_device_config dev_conf;
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const struct {
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int tx_out;
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int rx_in;
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int rts_out;
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int cts_in;
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} signals;
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const struct {
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int tx;
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int rx;
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int rts;
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int cts;
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} pins;
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const struct esp32_peripheral peripheral;
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const struct {
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int source;
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int line;
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} irq;
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};
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/* driver data */
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struct uart_esp32_data {
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struct uart_config uart_config;
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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uart_irq_callback_user_data_t irq_cb;
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void *irq_cb_data;
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#endif
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};
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#define DEV_CFG(dev) \
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((const struct uart_esp32_config *const)(dev)->config->config_info)
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#define DEV_DATA(dev) \
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((struct uart_esp32_data *)(dev)->driver_data)
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#define DEV_BASE(dev) \
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((volatile struct uart_esp32_regs_t *)(DEV_CFG(dev))->dev_conf.base)
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#define UART_TXFIFO_COUNT(status_reg) ((status_reg >> 16) & 0xFF)
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#define UART_RXFIFO_COUNT(status_reg) ((status_reg >> 0) & 0xFF)
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#define UART_FIFO_LIMIT 127U
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#define UART_TX_FIFO_THRESH 0x1
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#define UART_RX_FIFO_THRESH 0x1
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#define UART_GET_PARITY_ERR(reg) ((reg >> 2) & 0x1)
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#define UART_GET_FRAME_ERR(reg) ((reg >> 3) & 0x1)
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#define UART_GET_PARITY(conf0_reg) ((conf0_reg >> 0) & 0x1)
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#define UART_GET_PARITY_EN(conf0_reg) ((conf0_reg >> 1) & 0x1)
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#define UART_GET_DATA_BITS(conf0_reg) ((conf0_reg >> 2) & 0x3)
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#define UART_GET_STOP_BITS(conf0_reg) ((conf0_reg >> 4) & 0x3)
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#define UART_GET_TX_FLOW(conf0_reg) ((conf0_reg >> 15) & 0x1)
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#define UART_GET_RX_FLOW(conf1_reg) ((conf1_reg >> 23) & 0x1)
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/* FIXME: This should be removed when interrupt support added to ESP32 dts */
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#define INST_0_ESPRESSIF_ESP32_UART_IRQ_0 12
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#define INST_1_ESPRESSIF_ESP32_UART_IRQ_0 17
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#define INST_2_ESPRESSIF_ESP32_UART_IRQ_0 18
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/* ESP-IDF Naming is not consistent for UART0 with UART1/2 */
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#define DPORT_UART0_CLK_EN DPORT_UART_CLK_EN
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#define DPORT_UART0_RST DPORT_UART_RST
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static int uart_esp32_poll_in(struct device *dev, unsigned char *p_char)
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{
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if (UART_RXFIFO_COUNT(DEV_BASE(dev)->status) == 0) {
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return -1;
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}
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*p_char = DEV_BASE(dev)->fifo;
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return 0;
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}
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static void uart_esp32_poll_out(struct device *dev,
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unsigned char c)
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{
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/* Wait for space in FIFO */
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while (UART_TXFIFO_COUNT(DEV_BASE(dev)->status) >= UART_FIFO_LIMIT) {
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; /* Wait */
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}
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/* Send a character */
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DEV_BASE(dev)->fifo = (u32_t)c;
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}
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static int uart_esp32_err_check(struct device *dev)
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{
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u32_t err = UART_GET_PARITY_ERR(DEV_BASE(dev)->int_st)
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| UART_GET_FRAME_ERR(DEV_BASE(dev)->int_st);
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return err;
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}
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static int uart_esp32_config_get(struct device *dev, struct uart_config *cfg)
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{
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struct uart_esp32_data *data = DEV_DATA(dev);
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cfg->baudrate = data->uart_config.baudrate;
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if (UART_GET_PARITY_EN(DEV_BASE(dev)->conf0)) {
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cfg->parity = UART_GET_PARITY(DEV_BASE(dev)->conf0);
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} else {
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cfg->parity = UART_CFG_PARITY_NONE;
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}
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cfg->stop_bits = UART_GET_STOP_BITS(DEV_BASE(dev)->conf0);
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cfg->data_bits = UART_GET_DATA_BITS(DEV_BASE(dev)->conf0);
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if (UART_GET_TX_FLOW(DEV_BASE(dev)->conf0)) {
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cfg->flow_ctrl = UART_CFG_FLOW_CTRL_RTS_CTS;
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}
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if (UART_GET_RX_FLOW(DEV_BASE(dev)->conf1)) {
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cfg->flow_ctrl = UART_CFG_FLOW_CTRL_DTR_DSR;
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}
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return 0;
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}
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static int uart_esp32_set_baudrate(struct device *dev, int baudrate)
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{
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u32_t sys_clk_freq = DEV_CFG(dev)->dev_conf.sys_clk_freq;
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u32_t clk_div = (((sys_clk_freq) << 4) / baudrate);
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while (UART_TXFIFO_COUNT(DEV_BASE(dev)->status)) {
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; /* Wait */
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}
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if (clk_div < 16) {
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return -EINVAL;
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}
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DEV_BASE(dev)->clk_div = ((clk_div >> 4) | (clk_div & 0xf));
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return 1;
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}
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static int uart_esp32_configure_pins(struct device *dev)
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{
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const struct uart_esp32_config *const cfg = DEV_CFG(dev);
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esp32_rom_gpio_matrix_out(cfg->pins.tx,
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cfg->signals.tx_out,
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false,
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false);
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esp32_rom_gpio_matrix_in(cfg->pins.rx,
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cfg->signals.rx_in,
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false);
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if (cfg->pins.cts) {
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esp32_rom_gpio_matrix_out(cfg->pins.cts,
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cfg->signals.cts_in,
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false,
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false);
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}
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if (cfg->pins.rts) {
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esp32_rom_gpio_matrix_in(cfg->pins.rts,
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cfg->signals.rts_out,
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false);
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}
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return 0;
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}
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static int uart_esp32_configure(struct device *dev,
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const struct uart_config *cfg)
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{
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u32_t conf0 = UART_TICK_REF_ALWAYS_ON;
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u32_t conf1 = (UART_RX_FIFO_THRESH << UART_RXFIFO_FULL_THRHD_S)
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| (UART_TX_FIFO_THRESH << UART_TXFIFO_EMPTY_THRHD_S);
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uart_esp32_configure_pins(dev);
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esp32_enable_peripheral(&DEV_CFG(dev)->peripheral);
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/*
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* Reset RX Buffer by reading all received bytes
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* Hardware Reset functionality can't be used with UART 1/2
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*/
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while (UART_RXFIFO_COUNT(DEV_BASE(dev)->status) != 0) {
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(void) DEV_BASE(dev)->fifo;
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}
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switch (cfg->parity) {
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case UART_CFG_PARITY_NONE:
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conf0 &= ~(UART_PARITY_EN);
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conf0 &= ~(UART_PARITY);
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break;
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case UART_CFG_PARITY_EVEN:
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conf0 &= ~(UART_PARITY);
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break;
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case UART_CFG_PARITY_ODD:
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conf0 |= UART_PARITY;
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break;
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default:
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return -ENOTSUP;
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}
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switch (cfg->stop_bits) {
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case UART_CFG_STOP_BITS_1:
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case UART_CFG_STOP_BITS_1_5:
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case UART_CFG_STOP_BITS_2:
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conf0 |= cfg->stop_bits << UART_STOP_BIT_NUM_S;
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break;
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default:
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return -ENOTSUP;
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}
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if (cfg->data_bits <= UART_CFG_DATA_BITS_8) {
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conf0 |= cfg->data_bits << UART_BIT_NUM_S;
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} else {
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return -ENOTSUP;
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}
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switch (cfg->flow_ctrl) {
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case UART_CFG_FLOW_CTRL_NONE:
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conf0 &= ~(UART_TX_FLOW_EN);
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conf1 &= ~(UART_RX_FLOW_EN);
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break;
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case UART_CFG_FLOW_CTRL_RTS_CTS:
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conf0 |= UART_TX_FLOW_EN;
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conf1 |= UART_RX_FLOW_EN;
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break;
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default:
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return -ENOTSUP;
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}
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if (uart_esp32_set_baudrate(dev, cfg->baudrate)) {
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DEV_DATA(dev)->uart_config.baudrate = cfg->baudrate;
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} else {
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return -ENOTSUP;
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}
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DEV_BASE(dev)->conf0 = conf0;
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DEV_BASE(dev)->conf1 = conf1;
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return 0;
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}
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static int uart_esp32_init(struct device *dev)
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{
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uart_esp32_configure(dev, &DEV_DATA(dev)->uart_config);
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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DEV_CFG(dev)->dev_conf.irq_config_func(dev);
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#endif
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return 0;
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}
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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static int uart_esp32_fifo_fill(struct device *dev,
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const u8_t *tx_data, int len)
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{
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u8_t num_tx = 0U;
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while ((len - num_tx > 0) &&
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UART_TXFIFO_COUNT(DEV_BASE(dev)->status) < UART_FIFO_LIMIT) {
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DEV_BASE(dev)->fifo = (u32_t)tx_data[num_tx++];
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}
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return num_tx;
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}
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static int uart_esp32_fifo_read(struct device *dev,
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u8_t *rx_data, const int len)
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{
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u8_t num_rx = 0U;
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while ((len - num_rx > 0) &&
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(UART_RXFIFO_COUNT(DEV_BASE(dev)->status) != 0)) {
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rx_data[num_rx++] = DEV_BASE(dev)->fifo;
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}
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return num_rx;
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}
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static void uart_esp32_irq_tx_enable(struct device *dev)
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{
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DEV_BASE(dev)->int_clr |= UART_TXFIFO_EMPTY_INT_ENA;
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DEV_BASE(dev)->int_ena |= UART_TXFIFO_EMPTY_INT_ENA;
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}
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static void uart_esp32_irq_tx_disable(struct device *dev)
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{
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DEV_BASE(dev)->int_ena &= ~(UART_TXFIFO_EMPTY_INT_ENA);
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}
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static int uart_esp32_irq_tx_ready(struct device *dev)
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{
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return (UART_TXFIFO_COUNT(DEV_BASE(dev)->status) < UART_FIFO_LIMIT);
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}
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static void uart_esp32_irq_rx_enable(struct device *dev)
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{
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DEV_BASE(dev)->int_clr |= UART_RXFIFO_FULL_INT_ENA;
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DEV_BASE(dev)->int_ena |= UART_RXFIFO_FULL_INT_ENA;
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}
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static void uart_esp32_irq_rx_disable(struct device *dev)
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{
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DEV_BASE(dev)->int_ena &= ~(UART_RXFIFO_FULL_INT_ENA);
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}
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static int uart_esp32_irq_tx_complete(struct device *dev)
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{
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/* check if TX FIFO is empty */
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return (UART_TXFIFO_COUNT(DEV_BASE(dev)->status) == 0 ? 1 : 0);
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}
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static int uart_esp32_irq_rx_ready(struct device *dev)
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{
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return (UART_RXFIFO_COUNT(DEV_BASE(dev)->status) > 0);
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}
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static void uart_esp32_irq_err_enable(struct device *dev)
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{
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/* enable framing, parity */
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DEV_BASE(dev)->int_ena |= UART_FRM_ERR_INT_ENA
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| UART_PARITY_ERR_INT_ENA;
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}
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static void uart_esp32_irq_err_disable(struct device *dev)
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{
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DEV_BASE(dev)->int_ena &= ~(UART_FRM_ERR_INT_ENA);
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DEV_BASE(dev)->int_ena &= ~(UART_PARITY_ERR_INT_ENA);
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}
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static int uart_esp32_irq_is_pending(struct device *dev)
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{
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return uart_esp32_irq_rx_ready(dev) || uart_esp32_irq_tx_ready(dev);
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}
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static int uart_esp32_irq_update(struct device *dev)
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{
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DEV_BASE(dev)->int_clr |= UART_RXFIFO_FULL_INT_ENA;
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DEV_BASE(dev)->int_clr |= UART_TXFIFO_EMPTY_INT_ENA;
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return 1;
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}
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static void uart_esp32_irq_callback_set(struct device *dev,
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uart_irq_callback_user_data_t cb,
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void *cb_data)
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{
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DEV_DATA(dev)->irq_cb = cb;
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DEV_DATA(dev)->irq_cb_data = cb_data;
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}
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void uart_esp32_isr(void *arg)
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{
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struct device *dev = arg;
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struct uart_esp32_data *data = DEV_DATA(dev);
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/* Verify if the callback has been registered */
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if (data->irq_cb) {
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data->irq_cb(data->irq_cb_data);
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}
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}
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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static const struct uart_driver_api uart_esp32_api = {
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.poll_in = uart_esp32_poll_in,
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.poll_out = uart_esp32_poll_out,
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.err_check = uart_esp32_err_check,
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.configure = uart_esp32_configure,
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.config_get = uart_esp32_config_get,
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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.fifo_fill = uart_esp32_fifo_fill,
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.fifo_read = uart_esp32_fifo_read,
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.irq_tx_enable = uart_esp32_irq_tx_enable,
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.irq_tx_disable = uart_esp32_irq_tx_disable,
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.irq_tx_ready = uart_esp32_irq_tx_ready,
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.irq_rx_enable = uart_esp32_irq_rx_enable,
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.irq_rx_disable = uart_esp32_irq_rx_disable,
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.irq_tx_complete = uart_esp32_irq_tx_complete,
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.irq_rx_ready = uart_esp32_irq_rx_ready,
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.irq_err_enable = uart_esp32_irq_err_enable,
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.irq_err_disable = uart_esp32_irq_err_disable,
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.irq_is_pending = uart_esp32_irq_is_pending,
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.irq_update = uart_esp32_irq_update,
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.irq_callback_set = uart_esp32_irq_callback_set,
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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};
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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#define ESP32_UART_IRQ_HANDLER_DECL(idx) \
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static void uart_esp32_irq_config_func_##idx(struct device *dev)
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#define ESP32_UART_IRQ_HANDLER_FUNC(idx) \
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.irq_config_func = uart_esp32_irq_config_func_##idx,
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#define ESP32_UART_IRQ_HANDLER(idx) \
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static void uart_esp32_irq_config_func_##idx(struct device *dev) \
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{ \
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esp32_rom_intr_matrix_set(0, ETS_UART##idx##_INTR_SOURCE, \
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INST_##idx##_ESPRESSIF_ESP32_UART_IRQ_0); \
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IRQ_CONNECT(INST_##idx##_ESPRESSIF_ESP32_UART_IRQ_0, \
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1, \
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uart_esp32_isr, \
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DEVICE_GET(uart_esp32_##idx), \
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0); \
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irq_enable(INST_##idx##_ESPRESSIF_ESP32_UART_IRQ_0); \
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}
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#else
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#define ESP32_UART_IRQ_HANDLER_DECL(idx)
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#define ESP32_UART_IRQ_HANDLER_FUNC(idx)
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#define ESP32_UART_IRQ_HANDLER(idx)
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#endif
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#define ESP32_UART_INIT(idx) \
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ESP32_UART_IRQ_HANDLER_DECL(idx); \
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static const struct uart_esp32_config uart_esp32_cfg_port_##idx = { \
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.dev_conf = { \
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.base = \
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(u8_t *)DT_INST_REG_ADDR(idx), \
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.sys_clk_freq = \
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DT_PROP(DT_INST(0, cadence_tensilica_xtensa_lx6), clock_frequency),\
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|
ESP32_UART_IRQ_HANDLER_FUNC(idx) \
|
|
}, \
|
|
\
|
|
.peripheral = { \
|
|
.clk = DPORT_UART##idx##_CLK_EN, \
|
|
.rst = DPORT_UART##idx##_RST, \
|
|
}, \
|
|
\
|
|
.signals = { \
|
|
.tx_out = U##idx##TXD_OUT_IDX, \
|
|
.rx_in = U##idx##RXD_IN_IDX, \
|
|
.rts_out = U##idx##RTS_OUT_IDX, \
|
|
.cts_in = U##idx##CTS_IN_IDX, \
|
|
}, \
|
|
\
|
|
.pins = { \
|
|
.tx = DT_INST_PROP(idx, tx_pin), \
|
|
.rx = DT_INST_PROP(idx, rx_pin), \
|
|
IF_ENABLED( \
|
|
DT_INST_PROP(idx, hw_flow_control), \
|
|
(.rts = DT_INST_PROP(idx, rts_pin), \
|
|
.cts = DT_INST_PROP(idx, cts_pin), \
|
|
)) \
|
|
}, \
|
|
\
|
|
.irq = { \
|
|
.source = ETS_UART##idx##_INTR_SOURCE, \
|
|
.line = INST_##idx##_ESPRESSIF_ESP32_UART_IRQ_0, \
|
|
} \
|
|
}; \
|
|
\
|
|
static struct uart_esp32_data uart_esp32_data_##idx = { \
|
|
.uart_config = { \
|
|
.baudrate = DT_INST_PROP(idx, current_speed),\
|
|
.parity = UART_CFG_PARITY_NONE, \
|
|
.stop_bits = UART_CFG_STOP_BITS_1, \
|
|
.data_bits = UART_CFG_DATA_BITS_8, \
|
|
.flow_ctrl = IS_ENABLED( \
|
|
DT_INST_PROP(idx, hw_flow_control)) ?\
|
|
UART_CFG_FLOW_CTRL_RTS_CTS : UART_CFG_FLOW_CTRL_NONE \
|
|
} \
|
|
}; \
|
|
\
|
|
DEVICE_AND_API_INIT(uart_esp32_##idx, \
|
|
DT_INST_LABEL(idx), \
|
|
uart_esp32_init, \
|
|
&uart_esp32_data_##idx, \
|
|
&uart_esp32_cfg_port_##idx, \
|
|
PRE_KERNEL_1, \
|
|
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
|
|
&uart_esp32_api); \
|
|
\
|
|
ESP32_UART_IRQ_HANDLER(idx)
|
|
|
|
#if DT_HAS_DRV_INST(0)
|
|
ESP32_UART_INIT(0);
|
|
#endif
|
|
|
|
#if DT_HAS_DRV_INST(1)
|
|
ESP32_UART_INIT(1);
|
|
#endif
|
|
|
|
#if DT_HAS_DRV_INST(2)
|
|
ESP32_UART_INIT(2);
|
|
#endif
|