65 lines
1.5 KiB
C
65 lines
1.5 KiB
C
/*
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* Copyright 2022, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/init.h>
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#if !defined(CONFIG_SOC_SERIES_LPC11U6X)
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#include <fsl_clock.h>
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#endif
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#define OFFSET(mux) (((mux) & 0xFFF00000) >> 20)
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#define TYPE(mux) (((mux) & 0xC0000) >> 18)
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#define IOCON_TYPE_D 0x0
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#define IOCON_TYPE_I 0x1
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#define IOCON_TYPE_A 0x2
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static volatile uint32_t *iocon =
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(volatile uint32_t *)DT_REG_ADDR(DT_NODELABEL(iocon));
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
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uintptr_t reg)
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{
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for (uint8_t i = 0; i < pin_cnt; i++) {
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uint32_t pin_mux = pins[i];
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uint32_t offset = OFFSET(pin_mux);
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/* Check if this is an analog or i2c type pin */
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switch (TYPE(pin_mux)) {
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case IOCON_TYPE_D:
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pin_mux &= Z_PINCTRL_IOCON_D_PIN_MASK;
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break;
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case IOCON_TYPE_I:
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pin_mux &= Z_PINCTRL_IOCON_I_PIN_MASK;
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break;
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case IOCON_TYPE_A:
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pin_mux &= Z_PINCTRL_IOCON_A_PIN_MASK;
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break;
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default:
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/* Should not occur */
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__ASSERT_NO_MSG(TYPE(pin_mux) <= IOCON_TYPE_A);
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}
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/* Set pinmux */
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*(iocon + offset) = pin_mux;
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}
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return 0;
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}
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#if defined(CONFIG_SOC_FAMILY_LPC) && !defined(CONFIG_SOC_SERIES_LPC11U6X)
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/* LPC family (except 11u6x) needs iocon clock to be enabled */
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static int pinctrl_clock_init(void)
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{
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/* Enable IOCon clock */
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CLOCK_EnableClock(kCLOCK_Iocon);
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return 0;
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}
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SYS_INIT(pinctrl_clock_init, PRE_KERNEL_1, 0);
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#endif /* CONFIG_SOC_FAMILY_LPC && !CONFIG_SOC_SERIES_LPC11U6X */
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