237 lines
7.3 KiB
C
237 lines
7.3 KiB
C
/*
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* Copyright (c) 2011-2014 Wind River Systems, Inc.
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* Copyright (c) 2017-2020 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Internal memory management interfaces implemented in x86_mmu.c.
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* None of these are application-facing, use only if you know what you are
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* doing!
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*/
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#ifndef ZEPHYR_ARCH_X86_INCLUDE_X86_MMU_H
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#define ZEPHYR_ARCH_X86_INCLUDE_X86_MMU_H
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#include <zephyr/kernel.h>
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#include <zephyr/arch/x86/mmustructs.h>
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#include <zephyr/sys/mem_manage.h>
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#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
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#define XD_SUPPORTED
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#define BITL BIT64
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#define PRI_ENTRY "0x%016llx"
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#else
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#define BITL BIT
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#define PRI_ENTRY "0x%08x"
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#endif
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/*
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* Common flags in the same bit position regardless of which structure level,
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* although not every flag is supported at every level, and some may be
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* ignored depending on the state of other bits (such as P or PS)
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*
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* These flags indicate bit position, and can be used for setting flags or
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* masks as needed.
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*/
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#define MMU_P BITL(0) /** Present */
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#define MMU_RW BITL(1) /** Read-Write */
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#define MMU_US BITL(2) /** User-Supervisor */
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#define MMU_PWT BITL(3) /** Page Write Through */
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#define MMU_PCD BITL(4) /** Page Cache Disable */
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#define MMU_A BITL(5) /** Accessed */
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#define MMU_D BITL(6) /** Dirty */
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#define MMU_PS BITL(7) /** Page Size (non PTE)*/
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#define MMU_PAT BITL(7) /** Page Attribute (PTE) */
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#define MMU_G BITL(8) /** Global */
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#ifdef XD_SUPPORTED
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#define MMU_XD BITL(63) /** Execute Disable */
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#else
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#define MMU_XD 0
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#endif
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/* Unused PTE bits ignored by the CPU, which we use for our own OS purposes.
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* These bits ignored for all paging modes.
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*/
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#define MMU_IGNORED0 BITL(9)
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#define MMU_IGNORED1 BITL(10)
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#define MMU_IGNORED2 BITL(11)
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/* Page fault error code flags. See Chapter 4.7 of the Intel SDM vol. 3A. */
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#define PF_P BIT(0) /* 0 Non-present page 1 Protection violation */
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#define PF_WR BIT(1) /* 0 Read 1 Write */
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#define PF_US BIT(2) /* 0 Supervisor mode 1 User mode */
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#define PF_RSVD BIT(3) /* 1 reserved bit set */
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#define PF_ID BIT(4) /* 1 instruction fetch */
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#define PF_PK BIT(5) /* 1 protection-key violation */
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#define PF_SGX BIT(15) /* 1 SGX-specific access control requirements */
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#ifndef _ASMLANGUAGE
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#ifdef CONFIG_EXCEPTION_DEBUG
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/**
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* Dump out page table entries for a particular virtual memory address
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*
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* For the provided memory address, dump out interesting information about
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* its mapping to the error log
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*
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* @param ptables Page tables to walk
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* @param virt Virtual address to inspect
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*/
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void z_x86_dump_mmu_flags(pentry_t *ptables, void *virt);
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/**
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* Fetch the page table entry for a virtual memory address
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*
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* @param paging_level [out] what paging level the entry was found at.
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* 0=toplevel
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* @param val Value stored in page table entry, with address and flags
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* @param ptables Toplevel pointer to page tables
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* @param virt Virtual address to lookup
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*/
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void z_x86_pentry_get(int *paging_level, pentry_t *val, pentry_t *ptables,
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void *virt);
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/**
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* Debug function for dumping out page tables
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*
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* Iterates through the entire linked set of page table structures,
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* dumping out codes for the configuration of each table entry.
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*
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* Entry codes:
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*
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* . - not present
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* w - present, writable, not executable
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* a - present, writable, executable
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* r - present, read-only, not executable
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* x - present, read-only, executable
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*
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* Entry codes in uppercase indicate that user mode may access.
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*
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* Color is used to indicate the physical mapping characteristics:
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*
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* yellow - Identity mapping (virt = phys)
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* green - Fixed virtual memory mapping (virt = phys + constant)
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* magenta - entry is child page table
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* cyan - General mapped memory
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*
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* @param ptables Top-level pointer to the page tables, as programmed in CR3
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*/
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void z_x86_dump_page_tables(pentry_t *ptables);
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#endif /* CONFIG_EXCEPTION_DEBUG */
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#ifdef CONFIG_HW_STACK_PROTECTION
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/* Legacy function - set identity-mapped MMU stack guard page to RO in the
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* kernel's page tables to prevent writes and generate an exception
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*/
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void z_x86_set_stack_guard(k_thread_stack_t *stack);
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#endif
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#ifdef CONFIG_USERSPACE
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#ifdef CONFIG_X86_KPTI
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/* Defined in linker script. Contains all the data that must be mapped
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* in a KPTI table even though US bit is not set (trampoline stack, GDT,
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* IDT, etc)
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*/
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extern uint8_t z_shared_kernel_page_start;
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#ifdef CONFIG_DEMAND_PAGING
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/* Called from page fault handler. ptables here is the ptage tables for the
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* faulting user thread and not the current set of page tables
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*/
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extern bool z_x86_kpti_is_access_ok(void *virt, pentry_t *ptables)
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#endif /* CONFIG_DEMAND_PAGING */
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#endif /* CONFIG_X86_KPTI */
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#endif /* CONFIG_USERSPACE */
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#ifdef CONFIG_X86_PAE
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#define PTABLES_ALIGN 0x1fU
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#else
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#define PTABLES_ALIGN 0xfffU
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#endif
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/* Set CR3 to a physical address. There must be a valid top-level paging
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* structure here or the CPU will triple fault. The incoming page tables must
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* have the same kernel mappings wrt supervisor mode. Don't use this function
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* unless you know exactly what you are doing.
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*/
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static inline void z_x86_cr3_set(uintptr_t phys)
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{
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__ASSERT((phys & PTABLES_ALIGN) == 0U, "unaligned page tables");
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#ifdef CONFIG_X86_64
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__asm__ volatile("movq %0, %%cr3\n\t" : : "r" (phys) : "memory");
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#else
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__asm__ volatile("movl %0, %%cr3\n\t" : : "r" (phys) : "memory");
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#endif
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}
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/* Return cr3 value, which is the physical (not virtual) address of the
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* current set of page tables
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*/
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static inline uintptr_t z_x86_cr3_get(void)
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{
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uintptr_t cr3;
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#ifdef CONFIG_X86_64
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__asm__ volatile("movq %%cr3, %0\n\t" : "=r" (cr3));
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#else
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__asm__ volatile("movl %%cr3, %0\n\t" : "=r" (cr3));
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#endif
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return cr3;
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}
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/* Return the virtual address of the page tables installed in this CPU in CR3 */
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static inline pentry_t *z_x86_page_tables_get(void)
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{
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return z_mem_virt_addr(z_x86_cr3_get());
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}
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/* Return cr2 value, which contains the page fault linear address.
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* See Section 6.15 of the IA32 Software Developer's Manual vol 3.
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* Used by page fault handling code.
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*/
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static inline void *z_x86_cr2_get(void)
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{
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void *cr2;
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#ifdef CONFIG_X86_64
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__asm__ volatile("movq %%cr2, %0\n\t" : "=r" (cr2));
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#else
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__asm__ volatile("movl %%cr2, %0\n\t" : "=r" (cr2));
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#endif
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return cr2;
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}
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/* Kernel's page table. This is in CR3 for all supervisor threads.
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* if KPTI is enabled, we switch to this when handling exceptions or syscalls
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*/
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extern pentry_t z_x86_kernel_ptables[];
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/* Get the page tables used by this thread during normal execution */
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static inline pentry_t *z_x86_thread_page_tables_get(struct k_thread *thread)
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{
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#if defined(CONFIG_USERSPACE) && !defined(CONFIG_X86_COMMON_PAGE_TABLE)
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if (!IS_ENABLED(CONFIG_X86_KPTI) ||
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(thread->base.user_options & K_USER) != 0U) {
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/* If KPTI is enabled, supervisor threads always use
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* the kernel's page tables and not the page tables associated
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* with their memory domain.
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*/
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return z_mem_virt_addr(thread->arch.ptables);
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}
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#endif
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return z_x86_kernel_ptables;
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}
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#ifdef CONFIG_SMP
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/* Handling function for TLB shootdown inter-processor interrupts. */
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void z_x86_tlb_ipi(const void *arg);
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#endif
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#ifdef CONFIG_X86_COMMON_PAGE_TABLE
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void z_x86_swap_update_common_page_table(struct k_thread *incoming);
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#endif
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/* Early-boot paging setup tasks, called from prep_c */
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void z_x86_mmu_init(void);
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#endif /* _ASMLANGUAGE */
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#endif /* ZEPHYR_ARCH_X86_INCLUDE_X86_MMU_H */
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