216 lines
6.7 KiB
C
216 lines
6.7 KiB
C
/*
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* Copyright (c) 2016 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Nios II specific kernel interface header
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* This header contains the Nios II specific kernel interface. It is
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* included by the generic kernel interface header (include/arch/cpu.h)
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*/
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#ifndef _ARCH_IFACE_H
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#define _ARCH_IFACE_H
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#include <system.h>
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#include <arch/nios2/asm_inline.h>
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#include "nios2.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define STACK_ALIGN 4
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#define _NANO_ERR_CPU_EXCEPTION (0) /* Any unhandled exception */
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#define _NANO_ERR_INVALID_TASK_EXIT (1) /* Invalid task exit */
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#define _NANO_ERR_STACK_CHK_FAIL (2) /* Stack corruption detected */
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#define _NANO_ERR_ALLOCATION_FAIL (3) /* Kernel Allocation Failure */
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#define _NANO_ERR_SPURIOUS_INT (4) /* Spurious interrupt */
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#define _NANO_ERR_KERNEL_OOPS (5) /* Kernel oops (fatal to thread) */
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#define _NANO_ERR_KERNEL_PANIC (6) /* Kernel panic (fatal to system) */
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/* APIs need to support non-byte addressable architectures */
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#define OCTET_TO_SIZEOFUNIT(X) (X)
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#define SIZEOFUNIT_TO_OCTET(X) (X)
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#ifndef _ASMLANGUAGE
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#include <zephyr/types.h>
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#include <irq.h>
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#include <sw_isr_table.h>
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/* physical/virtual address types required by the kernel */
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typedef unsigned int paddr_t;
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typedef unsigned int vaddr_t;
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/**
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* Configure a static interrupt.
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*
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* All arguments must be computable by the compiler at build time.
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*
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* Internally this function does a few things:
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*
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* 1. The enum statement has no effect but forces the compiler to only
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* accept constant values for the irq_p parameter, very important as the
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* numerical IRQ line is used to create a named section.
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*
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* 2. An instance of struct _isr_table_entry is created containing the ISR and
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* its parameter. If you look at how _sw_isr_table is created, each entry in
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* the array is in its own section named by the IRQ line number. What we are
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* doing here is to override one of the default entries (which points to the
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* spurious IRQ handler) with what was supplied here.
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*
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* There is no notion of priority with the Nios II internal interrupt
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* controller and no flags are currently supported.
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*
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* @param irq_p IRQ line number
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* @param priority_p Interrupt priority (ignored)
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* @param isr_p Interrupt service routine
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* @param isr_param_p ISR parameter
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* @param flags_p IRQ triggering options (currently unused)
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*
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* @return The vector assigned to this interrupt
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*/
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#define _ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \
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({ \
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_ISR_DECLARE(irq_p, 0, isr_p, isr_param_p); \
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irq_p; \
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})
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extern void _irq_spurious(void *unused);
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static ALWAYS_INLINE unsigned int _arch_irq_lock(void)
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{
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unsigned int key, tmp;
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__asm__ volatile (
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"rdctl %[key], status\n\t"
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"movi %[tmp], -2\n\t"
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"and %[tmp], %[key], %[tmp]\n\t"
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"wrctl status, %[tmp]\n\t"
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: [key] "=r" (key), [tmp] "=r" (tmp)
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: : "memory");
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return key;
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}
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static ALWAYS_INLINE void _arch_irq_unlock(unsigned int key)
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{
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/* If the CPU is built without certain features, then
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* the only writable bit in the status register is PIE
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* in which case we can just write the value stored in key,
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* all the other writable bits will be the same.
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*
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* If not, other stuff could have changed and we need to
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* specifically flip just that bit.
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*/
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#if (ALT_CPU_NUM_OF_SHADOW_REG_SETS > 0) || \
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(defined ALT_CPU_EIC_PRESENT) || \
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(defined ALT_CPU_MMU_PRESENT) || \
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(defined ALT_CPU_MPU_PRESENT)
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__asm__ volatile (
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"andi %[key], %[key], 1\n\t"
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"beq %[key], zero, 1f\n\t"
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"rdctl %[key], status\n\t"
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"ori %[key], %[key], 1\n\t"
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"wrctl status, %[key]\n\t"
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"1:\n\t"
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: [key] "+r" (key)
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: : "memory");
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#else
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__asm__ volatile (
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"wrctl status, %[key]"
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: : [key] "r" (key)
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: "memory");
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#endif
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}
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void _arch_irq_enable(unsigned int irq);
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void _arch_irq_disable(unsigned int irq);
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struct __esf {
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u32_t ra; /* return address r31 */
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u32_t r1; /* at */
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u32_t r2; /* return value */
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u32_t r3; /* return value */
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u32_t r4; /* register args */
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u32_t r5; /* register args */
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u32_t r6; /* register args */
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u32_t r7; /* register args */
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u32_t r8; /* Caller-saved general purpose */
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u32_t r9; /* Caller-saved general purpose */
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u32_t r10; /* Caller-saved general purpose */
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u32_t r11; /* Caller-saved general purpose */
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u32_t r12; /* Caller-saved general purpose */
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u32_t r13; /* Caller-saved general purpose */
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u32_t r14; /* Caller-saved general purpose */
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u32_t r15; /* Caller-saved general purpose */
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u32_t estatus;
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u32_t instr; /* Instruction being executed when exc occurred */
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};
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typedef struct __esf NANO_ESF;
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extern const NANO_ESF _default_esf;
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FUNC_NORETURN void _SysFatalErrorHandler(unsigned int reason,
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const NANO_ESF *esf);
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FUNC_NORETURN void _NanoFatalErrorHandler(unsigned int reason,
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const NANO_ESF *esf);
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enum nios2_exception_cause {
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NIOS2_EXCEPTION_UNKNOWN = -1,
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NIOS2_EXCEPTION_RESET = 0,
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NIOS2_EXCEPTION_CPU_ONLY_RESET_REQUEST = 1,
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NIOS2_EXCEPTION_INTERRUPT = 2,
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NIOS2_EXCEPTION_TRAP_INST = 3,
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NIOS2_EXCEPTION_UNIMPLEMENTED_INST = 4,
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NIOS2_EXCEPTION_ILLEGAL_INST = 5,
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NIOS2_EXCEPTION_MISALIGNED_DATA_ADDR = 6,
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NIOS2_EXCEPTION_MISALIGNED_TARGET_PC = 7,
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NIOS2_EXCEPTION_DIVISION_ERROR = 8,
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NIOS2_EXCEPTION_SUPERVISOR_ONLY_INST_ADDR = 9,
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NIOS2_EXCEPTION_SUPERVISOR_ONLY_INST = 10,
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NIOS2_EXCEPTION_SUPERVISOR_ONLY_DATA_ADDR = 11,
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NIOS2_EXCEPTION_TLB_MISS = 12,
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NIOS2_EXCEPTION_TLB_EXECUTE_PERM_VIOLATION = 13,
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NIOS2_EXCEPTION_TLB_READ_PERM_VIOLATION = 14,
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NIOS2_EXCEPTION_TLB_WRITE_PERM_VIOLATION = 15,
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NIOS2_EXCEPTION_MPU_INST_REGION_VIOLATION = 16,
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NIOS2_EXCEPTION_MPU_DATA_REGION_VIOLATION = 17,
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NIOS2_EXCEPTION_ECC_TLB_ERR = 18,
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NIOS2_EXCEPTION_ECC_FETCH_ERR = 19,
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NIOS2_EXCEPTION_ECC_REGISTER_FILE_ERR = 20,
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NIOS2_EXCEPTION_ECC_DATA_ERR = 21,
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NIOS2_EXCEPTION_ECC_DATA_CACHE_WRITEBACK_ERR = 22
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};
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/* Bitfield indicating which exception cause codes report a valid
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* badaddr register. NIOS2_EXCEPTION_TLB_MISS and NIOS2_EXCEPTION_ECC_TLB_ERR
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* are deliberately not included here, you need to check if TLBMISC.D=1
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*/
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#define NIOS2_BADADDR_CAUSE_MASK \
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(BIT(NIOS2_EXCEPTION_SUPERVISOR_ONLY_DATA_ADDR) | \
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BIT(NIOS2_EXCEPTION_MISALIGNED_DATA_ADDR) | \
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BIT(NIOS2_EXCEPTION_MISALIGNED_TARGET_PC) | \
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BIT(NIOS2_EXCEPTION_TLB_READ_PERM_VIOLATION) | \
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BIT(NIOS2_EXCEPTION_TLB_WRITE_PERM_VIOLATION) | \
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BIT(NIOS2_EXCEPTION_MPU_DATA_REGION_VIOLATION) | \
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BIT(NIOS2_EXCEPTION_ECC_DATA_ERR))
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extern u32_t _timer_cycle_get_32(void);
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#define _arch_k_cycle_get_32() _timer_cycle_get_32()
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif
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