106 lines
1.8 KiB
Plaintext
106 lines
1.8 KiB
Plaintext
# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_ESP32C2 || SOC_SERIES_ESP32C3 || SOC_SERIES_ESP32C6
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config GEN_ISR_TABLES
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default y
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config GEN_SW_ISR_TABLE
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default y
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config GEN_IRQ_VECTOR_TABLE
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default n
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config DYNAMIC_INTERRUPTS
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default y
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config ISR_STACK_SIZE
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default 2048
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config ATOMIC_OPERATIONS_C
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default y
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config XTAL_FREQ_HZ
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int
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default $(dt_node_int_prop_int,/cpus/cpu@0,xtal-freq)
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 10400000 if XTAL_FREQ_HZ = 26000000
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default 16000000 if XTAL_FREQ_HZ = 40000000
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config SYS_CLOCK_TICKS_PER_SEC
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default 1000
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config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE
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default n
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config SOC_FLASH_ESP32
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default y
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if BOOTLOADER_MCUBOOT
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config HAS_FLASH_LOAD_OFFSET
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default y
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config MCUBOOT_GENERATE_UNSIGNED_IMAGE
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default y
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config MCUBOOT_GENERATE_CONFIRMED_IMAGE
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default y
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config ROM_START_OFFSET
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default 0x20
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endif # BOOTLOADER_MCUBOOT
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endif # SOC_SERIES_ESP32C2 || SOC_SERIES_ESP32C3 || SOC_SERIES_ESP32C6
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if SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
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# Xtensa default options for ESP32 family
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config XTENSA_RESET_VECTOR
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default n
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config XTENSA_USE_CORE_CRT1
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default n
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config GEN_ISR_TABLES
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default y
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config GEN_IRQ_VECTOR_TABLE
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default n
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config CLOCK_CONTROL
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default y
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config SOC_FLASH_ESP32
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default y
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
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config XTENSA_CCOUNT_HZ
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default SYS_CLOCK_HW_CYCLES_PER_SEC
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config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE
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default n
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if BOOTLOADER_MCUBOOT
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config HAS_FLASH_LOAD_OFFSET
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default y
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config MCUBOOT_GENERATE_UNSIGNED_IMAGE
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default y
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config MCUBOOT_GENERATE_CONFIRMED_IMAGE
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default y
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config ROM_START_OFFSET
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default 0x20
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endif # BOOTLOADER_MCUBOOT
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endif # SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
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