zephyr/drivers/i2s/Kconfig.stm32

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# STM32 I2S driver configuration options
# Copyright (c) 2018 STMicroelectronics
# SPDX-License-Identifier: Apache-2.0
menuconfig I2S_STM32
bool "STM32 MCU I2S controller driver"
depends on SOC_SERIES_STM32F4X
select DMA
help
Enable I2S support on the STM32 family of processors.
(Tested on the STM32F4 series)
if I2S_STM32
config I2S_STM32_RX_BLOCK_COUNT
int "RX queue length"
default 4
config I2S_STM32_TX_BLOCK_COUNT
int "TX queue length"
default 4
config I2S_STM32_USE_PLLI2S_ENABLE
bool "Enable usage of PLL"
help
Enable it if I2S clock should be provided by the PLLI2S.
If not enabled the clock will be provided by HSI/HSE.
config I2S_STM32_PLLI2S_PLLM
int "Division factor for PLLI2S VCO input clock"
depends on I2S_STM32_USE_PLLI2S_ENABLE
default 8
range 2 63
help
Division factor for the audio PLL (PLLI2S) VCO input clock.
PLLM factor should be selected to ensure that the VCO
input frequency ranges from 1 to 2 MHz. It is recommended
to select a frequency of 2 MHz to limit PLL jitter.
Allowed values: 2-63
config I2S_STM32_PLLI2S_PLLN
int "Multiplier factor for PLLI2S VCO output clock"
depends on I2S_STM32_USE_PLLI2S_ENABLE
default 56
range 50 432
help
Multiply factor for the audio PLL (PLLI2S) VCO output clock.
PLLN factor should be selected to ensure that the VCO
output frequency ranges from 100 to 432 MHz.
Allowed values: 50-432
config I2S_STM32_PLLI2S_PLLR
int "Division factor for I2S clock"
depends on I2S_STM32_USE_PLLI2S_ENABLE
default 7
range 2 7
help
Division factor for the I2S clock.
PLLR factor should be selected to ensure that the I2S clock
frequency is less than or equal to 192MHz.
Allowed values: 2-7
config I2S_1
bool "I2S port 1"
help
Enable I2S controller port 1.
config I2S_2
bool "I2S port 2"
help
Enable I2S controller port 2.
config I2S_3
bool "I2S port 3"
help
Enable I2S controller port 3.
config I2S_4
bool "I2S port 4"
help
Enable I2S controller port 4.
config I2S_5
bool "I2S port 5"
help
Enable I2S controller port 5.
endif # I2S_STM32