509 lines
15 KiB
C
509 lines
15 KiB
C
/*
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* Copyright (c) 2023 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT ambiq_spi
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(spi_ambiq);
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#include <zephyr/drivers/spi.h>
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#include <zephyr/drivers/spi/rtio.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/kernel.h>
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#include <zephyr/sys/byteorder.h>
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#include <zephyr/pm/device.h>
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#include <zephyr/pm/policy.h>
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#include <zephyr/pm/device_runtime.h>
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#include <stdlib.h>
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#include <errno.h>
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#include "spi_context.h"
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#include <am_mcu_apollo.h>
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#define PWRCTRL_MAX_WAIT_US 5
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typedef int (*ambiq_spi_pwr_func_t)(void);
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struct spi_ambiq_config {
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uint32_t base;
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int size;
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uint32_t clock_freq;
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const struct pinctrl_dev_config *pcfg;
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ambiq_spi_pwr_func_t pwr_func;
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void (*irq_config_func)(void);
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};
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struct spi_ambiq_data {
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struct spi_context ctx;
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am_hal_iom_config_t iom_cfg;
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void *iom_handler;
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int inst_idx;
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bool cont;
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};
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typedef void (*spi_context_update_trx)(struct spi_context *ctx, uint8_t dfs, uint32_t len);
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#define SPI_WORD_SIZE 8
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#define SPI_CS_INDEX 3
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#ifdef CONFIG_SPI_AMBIQ_DMA
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static __aligned(32) struct {
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__aligned(32) uint32_t buf[CONFIG_SPI_DMA_TCB_BUFFER_SIZE];
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} spi_dma_tcb_buf[DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT)] __attribute__((__section__(".nocache")));
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static void spi_ambiq_callback(void *callback_ctxt, uint32_t status)
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{
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const struct device *dev = callback_ctxt;
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struct spi_ambiq_data *data = dev->data;
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struct spi_context *ctx = &data->ctx;
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/* de-assert cs until transfer finished and no need to hold cs */
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if (!data->cont) {
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spi_context_cs_control(ctx, false);
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}
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spi_context_complete(ctx, dev, (status == AM_HAL_STATUS_SUCCESS) ? 0 : -EIO);
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}
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#endif
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static void spi_ambiq_reset(const struct device *dev)
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{
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struct spi_ambiq_data *data = dev->data;
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struct spi_context *ctx = &data->ctx;
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/* cancel timed out transaction */
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am_hal_iom_disable(data->iom_handler);
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/* NULL config to trigger reconfigure on next xfer */
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ctx->config = NULL;
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spi_context_cs_control(ctx, false);
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/* signal any thread waiting on sync semaphore */
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spi_context_complete(ctx, dev, -ETIMEDOUT);
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/* clean up for next xfer */
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k_sem_reset(&ctx->sync);
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}
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static void spi_ambiq_isr(const struct device *dev)
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{
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uint32_t ui32Status;
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struct spi_ambiq_data *data = dev->data;
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am_hal_iom_interrupt_status_get(data->iom_handler, false, &ui32Status);
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am_hal_iom_interrupt_clear(data->iom_handler, ui32Status);
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am_hal_iom_interrupt_service(data->iom_handler, ui32Status);
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}
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static int spi_config(const struct device *dev, const struct spi_config *config)
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{
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struct spi_ambiq_data *data = dev->data;
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const struct spi_ambiq_config *cfg = dev->config;
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struct spi_context *ctx = &(data->ctx);
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data->iom_cfg.eInterfaceMode = AM_HAL_IOM_SPI_MODE;
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int ret = 0;
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if (spi_context_configured(ctx, config)) {
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/* Already configured. No need to do it again. */
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return 0;
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}
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if (SPI_WORD_SIZE_GET(config->operation) != SPI_WORD_SIZE) {
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LOG_ERR("Word size must be %d", SPI_WORD_SIZE);
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return -ENOTSUP;
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}
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if ((config->operation & SPI_LINES_MASK) != SPI_LINES_SINGLE) {
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LOG_ERR("Only supports single mode");
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return -ENOTSUP;
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}
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if (config->operation & SPI_LOCK_ON) {
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LOG_ERR("Lock On not supported");
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return -ENOTSUP;
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}
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if (config->operation & SPI_TRANSFER_LSB) {
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LOG_ERR("LSB first not supported");
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return -ENOTSUP;
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}
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if (config->operation & SPI_MODE_CPOL) {
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if (config->operation & SPI_MODE_CPHA) {
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data->iom_cfg.eSpiMode = AM_HAL_IOM_SPI_MODE_3;
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} else {
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data->iom_cfg.eSpiMode = AM_HAL_IOM_SPI_MODE_2;
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}
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} else {
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if (config->operation & SPI_MODE_CPHA) {
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data->iom_cfg.eSpiMode = AM_HAL_IOM_SPI_MODE_1;
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} else {
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data->iom_cfg.eSpiMode = AM_HAL_IOM_SPI_MODE_0;
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}
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}
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if (config->operation & SPI_OP_MODE_SLAVE) {
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LOG_ERR("Slave mode not supported");
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return -ENOTSUP;
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}
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if (config->operation & SPI_MODE_LOOP) {
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LOG_ERR("Loopback mode not supported");
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return -ENOTSUP;
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}
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if (cfg->clock_freq > AM_HAL_IOM_MAX_FREQ) {
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LOG_ERR("Clock frequency too high");
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return -ENOTSUP;
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}
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/* Select slower of two: SPI bus frequency for SPI device or SPI master clock frequency */
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data->iom_cfg.ui32ClockFreq =
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(config->frequency ? MIN(config->frequency, cfg->clock_freq) : cfg->clock_freq);
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ctx->config = config;
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#ifdef CONFIG_SPI_AMBIQ_DMA
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data->iom_cfg.pNBTxnBuf = spi_dma_tcb_buf[data->inst_idx].buf;
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data->iom_cfg.ui32NBTxnBufLength = CONFIG_SPI_DMA_TCB_BUFFER_SIZE;
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#endif
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/* Disable IOM instance as it cannot be configured when enabled*/
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ret = am_hal_iom_disable(data->iom_handler);
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ret = am_hal_iom_configure(data->iom_handler, &data->iom_cfg);
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ret = am_hal_iom_enable(data->iom_handler);
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return ret;
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}
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static int spi_ambiq_xfer_half_duplex(const struct device *dev, am_hal_iom_dir_e dir)
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{
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am_hal_iom_transfer_t trans = {0};
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struct spi_ambiq_data *data = dev->data;
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struct spi_context *ctx = &data->ctx;
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bool is_last = false;
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uint32_t rem_num, cur_num = 0;
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int ret = 0;
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spi_context_update_trx ctx_update;
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if (dir == AM_HAL_IOM_FULLDUPLEX) {
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return -EINVAL;
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} else if (dir == AM_HAL_IOM_RX) {
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trans.eDirection = AM_HAL_IOM_RX;
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ctx_update = spi_context_update_rx;
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} else {
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trans.eDirection = AM_HAL_IOM_TX;
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ctx_update = spi_context_update_tx;
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}
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if (dir == AM_HAL_IOM_RX) {
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rem_num = ctx->rx_len;
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} else {
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rem_num = ctx->tx_len;
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}
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while (rem_num) {
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cur_num = (rem_num > AM_HAL_IOM_MAX_TXNSIZE_SPI) ? AM_HAL_IOM_MAX_TXNSIZE_SPI
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: rem_num;
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trans.ui32NumBytes = cur_num;
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trans.pui32TxBuffer = (uint32_t *)ctx->tx_buf;
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trans.pui32RxBuffer = (uint32_t *)ctx->rx_buf;
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ctx_update(ctx, 1, cur_num);
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if ((!spi_context_tx_buf_on(ctx)) && (!spi_context_rx_buf_on(ctx))) {
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is_last = true;
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}
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#ifdef CONFIG_SPI_AMBIQ_DMA
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if (AM_HAL_STATUS_SUCCESS !=
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am_hal_iom_nonblocking_transfer(data->iom_handler, &trans,
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((is_last == true) ? spi_ambiq_callback : NULL),
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(void *)dev)) {
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return -EIO;
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}
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if (is_last) {
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ret = spi_context_wait_for_completion(ctx);
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}
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#else
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ret = am_hal_iom_blocking_transfer(data->iom_handler, &trans);
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#endif
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rem_num -= cur_num;
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if (ret != 0) {
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return -EIO;
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}
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}
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return 0;
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}
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static int spi_ambiq_xfer_full_duplex(const struct device *dev)
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{
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am_hal_iom_transfer_t trans = {0};
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struct spi_ambiq_data *data = dev->data;
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struct spi_context *ctx = &data->ctx;
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bool trx_once = (ctx->tx_len == ctx->rx_len);
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int ret = 0;
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/* Tx and Rx length must be the same for am_hal_iom_spi_blocking_fullduplex */
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trans.eDirection = AM_HAL_IOM_FULLDUPLEX;
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trans.ui32NumBytes = MIN(ctx->rx_len, ctx->tx_len);
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trans.pui32RxBuffer = (uint32_t *)ctx->rx_buf;
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trans.pui32TxBuffer = (uint32_t *)ctx->tx_buf;
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spi_context_update_tx(ctx, 1, trans.ui32NumBytes);
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spi_context_update_rx(ctx, 1, trans.ui32NumBytes);
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ret = am_hal_iom_spi_blocking_fullduplex(data->iom_handler, &trans);
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if (ret != 0) {
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return -EIO;
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}
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/* Transfer the remaining bytes */
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if (!trx_once) {
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spi_context_update_trx ctx_update;
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if (ctx->tx_len) {
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trans.eDirection = AM_HAL_IOM_TX;
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trans.ui32NumBytes = ctx->tx_len;
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trans.pui32TxBuffer = (uint32_t *)ctx->tx_buf;
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ctx_update = spi_context_update_tx;
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} else {
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trans.eDirection = AM_HAL_IOM_RX;
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trans.ui32NumBytes = ctx->rx_len;
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trans.pui32RxBuffer = (uint32_t *)ctx->rx_buf;
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ctx_update = spi_context_update_rx;
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}
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ret = am_hal_iom_blocking_transfer(data->iom_handler, &trans);
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ctx_update(ctx, 1, trans.ui32NumBytes);
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if (ret != 0) {
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return -EIO;
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}
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}
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return 0;
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}
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static int spi_ambiq_xfer(const struct device *dev, const struct spi_config *config)
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{
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struct spi_ambiq_data *data = dev->data;
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struct spi_context *ctx = &data->ctx;
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int ret = 0;
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data->cont = (config->operation & SPI_HOLD_ON_CS) ? true : false;
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spi_context_cs_control(ctx, true);
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while (1) {
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if (spi_context_tx_buf_on(ctx) && spi_context_rx_buf_on(ctx)) {
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if (ctx->rx_buf == ctx->tx_buf) {
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spi_context_update_rx(ctx, 1, ctx->rx_len);
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} else if (!(config->operation & SPI_HALF_DUPLEX)) {
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ret = spi_ambiq_xfer_full_duplex(dev);
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if (ret != 0) {
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spi_ambiq_reset(dev);
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LOG_ERR("SPI full-duplex comm error: %d", ret);
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return ret;
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}
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}
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}
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if (spi_context_tx_on(ctx)) {
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if (ctx->tx_buf == NULL) {
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spi_context_update_tx(ctx, 1, ctx->tx_len);
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} else {
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ret = spi_ambiq_xfer_half_duplex(dev, AM_HAL_IOM_TX);
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if (ret != 0) {
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spi_ambiq_reset(dev);
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LOG_ERR("SPI TX comm error: %d", ret);
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return ret;
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}
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}
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} else if (spi_context_rx_on(ctx)) {
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if (ctx->rx_buf == NULL) {
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spi_context_update_rx(ctx, 1, ctx->rx_len);
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} else {
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ret = spi_ambiq_xfer_half_duplex(dev, AM_HAL_IOM_RX);
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if (ret != 0) {
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spi_ambiq_reset(dev);
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LOG_ERR("SPI Rx comm error: %d", ret);
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return ret;
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}
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}
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} else {
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break;
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}
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}
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#ifndef CONFIG_SPI_AMBIQ_DMA
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if (!data->cont) {
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spi_context_cs_control(ctx, false);
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spi_context_complete(ctx, dev, ret);
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}
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#endif
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return ret;
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}
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static int spi_ambiq_transceive(const struct device *dev, const struct spi_config *config,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs)
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{
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struct spi_ambiq_data *data = dev->data;
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int ret;
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if (!tx_bufs && !rx_bufs) {
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return 0;
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}
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ret = pm_device_runtime_get(dev);
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if (ret < 0) {
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LOG_ERR("pm_device_runtime_get failed: %d", ret);
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}
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/* context setup */
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spi_context_lock(&data->ctx, false, NULL, NULL, config);
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ret = spi_config(dev, config);
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if (ret) {
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spi_context_release(&data->ctx, ret);
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return ret;
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}
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spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, 1);
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ret = spi_ambiq_xfer(dev, config);
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spi_context_release(&data->ctx, ret);
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/* Use async put to avoid useless device suspension/resumption
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* when doing consecutive transmission.
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*/
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ret = pm_device_runtime_put_async(dev, K_MSEC(2));
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if (ret < 0) {
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LOG_ERR("pm_device_runtime_put failed: %d", ret);
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}
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return ret;
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}
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static int spi_ambiq_release(const struct device *dev, const struct spi_config *config)
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{
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struct spi_ambiq_data *data = dev->data;
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am_hal_iom_status_t iom_status;
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am_hal_iom_status_get(data->iom_handler, &iom_status);
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if ((iom_status.bStatIdle != IOM0_STATUS_IDLEST_IDLE) ||
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(iom_status.bStatCmdAct == IOM0_STATUS_CMDACT_ACTIVE) ||
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(iom_status.ui32NumPendTransactions)) {
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return -EBUSY;
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}
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spi_context_unlock_unconditionally(&data->ctx);
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return 0;
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}
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static const struct spi_driver_api spi_ambiq_driver_api = {
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.transceive = spi_ambiq_transceive,
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#ifdef CONFIG_SPI_RTIO
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.iodev_submit = spi_rtio_iodev_default_submit,
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#endif
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.release = spi_ambiq_release,
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};
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static int spi_ambiq_init(const struct device *dev)
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{
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struct spi_ambiq_data *data = dev->data;
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const struct spi_ambiq_config *cfg = dev->config;
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int ret = 0;
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if (AM_HAL_STATUS_SUCCESS !=
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am_hal_iom_initialize((cfg->base - IOM0_BASE) / cfg->size, &data->iom_handler)) {
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LOG_ERR("Fail to initialize SPI\n");
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return -ENXIO;
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}
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ret = cfg->pwr_func();
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ret |= pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
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ret |= spi_context_cs_configure_all(&data->ctx);
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if (ret < 0) {
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LOG_ERR("Fail to config SPI pins\n");
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goto end;
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}
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#ifdef CONFIG_SPI_AMBIQ_DMA
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am_hal_iom_interrupt_clear(data->iom_handler, AM_HAL_IOM_INT_CQUPD | AM_HAL_IOM_INT_ERR);
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am_hal_iom_interrupt_enable(data->iom_handler, AM_HAL_IOM_INT_CQUPD | AM_HAL_IOM_INT_ERR);
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cfg->irq_config_func();
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#endif
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end:
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if (ret < 0) {
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am_hal_iom_uninitialize(data->iom_handler);
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} else {
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spi_context_unlock_unconditionally(&data->ctx);
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}
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return ret;
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}
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#ifdef CONFIG_PM_DEVICE
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static int spi_ambiq_pm_action(const struct device *dev, enum pm_device_action action)
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{
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struct spi_ambiq_data *data = dev->data;
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uint32_t ret;
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am_hal_sysctrl_power_state_e status;
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switch (action) {
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case PM_DEVICE_ACTION_RESUME:
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status = AM_HAL_SYSCTRL_WAKE;
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break;
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case PM_DEVICE_ACTION_SUSPEND:
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status = AM_HAL_SYSCTRL_DEEPSLEEP;
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break;
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default:
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return -ENOTSUP;
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}
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ret = am_hal_iom_power_ctrl(data->iom_handler, status, true);
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if (ret != AM_HAL_STATUS_SUCCESS) {
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LOG_ERR("am_hal_iom_power_ctrl failed: %d", ret);
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return -EPERM;
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} else {
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return 0;
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}
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}
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#endif /* CONFIG_PM_DEVICE */
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#define AMBIQ_SPI_INIT(n) \
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PINCTRL_DT_INST_DEFINE(n); \
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static int pwr_on_ambiq_spi_##n(void) \
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{ \
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uint32_t addr = DT_REG_ADDR(DT_INST_PHANDLE(n, ambiq_pwrcfg)) + \
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DT_INST_PHA(n, ambiq_pwrcfg, offset); \
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sys_write32((sys_read32(addr) | DT_INST_PHA(n, ambiq_pwrcfg, mask)), addr); \
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k_busy_wait(PWRCTRL_MAX_WAIT_US); \
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return 0; \
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} \
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static void spi_irq_config_func_##n(void) \
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{ \
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IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), spi_ambiq_isr, \
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DEVICE_DT_INST_GET(n), 0); \
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irq_enable(DT_INST_IRQN(n)); \
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}; \
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static struct spi_ambiq_data spi_ambiq_data##n = { \
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SPI_CONTEXT_INIT_LOCK(spi_ambiq_data##n, ctx), \
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SPI_CONTEXT_INIT_SYNC(spi_ambiq_data##n, ctx), \
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SPI_CONTEXT_CS_GPIOS_INITIALIZE(DT_DRV_INST(n), ctx).inst_idx = n}; \
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|
static const struct spi_ambiq_config spi_ambiq_config##n = { \
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|
.base = DT_INST_REG_ADDR(n), \
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|
.size = DT_INST_REG_SIZE(n), \
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|
.clock_freq = DT_INST_PROP(n, clock_frequency), \
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|
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
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|
.irq_config_func = spi_irq_config_func_##n, \
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|
.pwr_func = pwr_on_ambiq_spi_##n}; \
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PM_DEVICE_DT_INST_DEFINE(n, spi_ambiq_pm_action); \
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DEVICE_DT_INST_DEFINE(n, spi_ambiq_init, PM_DEVICE_DT_INST_GET(n), &spi_ambiq_data##n, \
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&spi_ambiq_config##n, POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, \
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|
&spi_ambiq_driver_api);
|
|
|
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DT_INST_FOREACH_STATUS_OKAY(AMBIQ_SPI_INIT)
|