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zephyr/arch/xtensa/core
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Guennadi Liakhovetski d676d469bd LLEXT: Xtensa: add support for L32R relocation 
When building LLEXT for Xtensa with custom sections the compiler
can leave unresolved references in them. Then this has to be done by
the LLEXT core during linking. This commit adds linking support for
the L32R Xtensa instruction.

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
 		2024-09-29 21:21:24 +02:00
..
offsets xtensa: mpu: enable userspace support 2024-03-19 22:17:34 -04:00
startup xtensa: rename files with hyphens to underscores 2023-12-13 09:41:24 +01:00
CMakeLists.txt xtensa: introduce prep_c for xtensa 2024-08-07 13:50:53 +02:00
README_MMU.txt everywhere: replace double words 2024-06-25 06:05:35 -04:00
README_WINDOWS.rst xtensa: rename files with hyphens to underscores 2023-12-13 09:41:24 +01:00
coredump.c xtensa: coredump: support dumping privilege stack 2024-09-21 11:29:39 +02:00
cpu_idle.c arch: use same syntax for custom arch calls 2024-08-12 12:43:36 +02:00
crt1.S xtensa: introduce prep_c for xtensa 2024-08-07 13:50:53 +02:00
debug_helpers_asm.S build: namespace the generated headers with `zephyr/` 2024-05-28 22:03:55 +02:00
elf.c LLEXT: Xtensa: add support for L32R relocation 2024-09-29 21:21:24 +02:00
fatal.c arch: xtensa: fatal: Comply with MISRA Rule 14.4 2024-06-17 17:46:16 -04:00
gdbstub.c arch: define `struct arch_esf` and deprecate `z_arch_esf_t` 2024-06-04 14:02:51 -05:00
gen_vectors.py arch/xtensa: Add automatic vector linkage generation 2024-05-22 13:39:47 -05:00
gen_zsr.py xtensa: make it work with TLB misses during interrupt handling 2024-06-15 04:44:48 -04:00
irq_manage.c xtensa: rename z_xtensa to simply xtensa 2023-12-13 09:41:24 +01:00
irq_offload.c arch: initialize irq_offload during boot, do not use SYS_INIT 2024-09-17 20:05:22 -04:00
mem_manage.c xtensa: move to use system cache API support for coherency 2024-02-03 13:42:33 -05:00
mmu.c xtensa: mmu: Fix rasid initial value 2024-03-14 13:24:41 -05:00
mpu.c xtensa: mpu: update hardware if manipulating current domain 2024-09-16 09:55:53 +02:00
prep_c.c cache: add new interface arch_cache_init() for initializing cache 2024-09-17 20:05:22 -04:00
ptables.c xtensa: mmu: fix page table initialization 2024-08-14 09:36:19 +02:00
smp.c arch: call arch_smp_init() directly, do not use SYS_INIT 2024-06-12 18:23:54 -04:00
syscall_helper.c xtensa: make arch_user_string_nlen actually work 2024-06-15 04:44:48 -04:00
thread.c arch: kernel: lib: toolchain: Standardize TLS keyword 2024-09-23 10:01:48 +02:00
timing.c
…
tls.c
…
userspace.S xtensa: make arch_user_string_nlen actually work 2024-06-15 04:44:48 -04:00
vector_handlers.c xtensa: core: Remove constant branch 2024-08-13 18:18:53 -04:00
window_vectors.S build: namespace the generated headers with `zephyr/` 2024-05-28 22:03:55 +02:00
xcc_stubs.c
…
xtensa_asm2_util.S xtensa: mmu: bail on semantic triple faults 2024-06-15 04:44:48 -04:00
xtensa_backtrace.c soc: xtensa/dc233c: remove xtensa_dc233c_stack_ptr_is_sane 2024-06-21 09:59:36 +02:00
xtensa_hifi.S build: namespace the generated headers with `zephyr/` 2024-05-28 22:03:55 +02:00
xtensa_intgen.py arch/xtensa: xtensa_intgen.py: Emit handlers for all levels 2024-05-20 20:50:55 -04:00
xtensa_intgen.tmpl
…