802 lines
22 KiB
C
802 lines
22 KiB
C
/*
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* Copyright (c) 2021, Linaro Limited.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT arm_cmsdk_uart
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/**
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* @brief Driver for UART on ARM CMSDK APB UART.
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*
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* UART has two wires for RX and TX, and does not provide CTS or RTS.
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/arch/cpu.h>
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#include <zephyr/drivers/clock_control/arm_clock_control.h>
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#include <zephyr/sys/__assert.h>
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#include <zephyr/init.h>
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#include <zephyr/drivers/uart.h>
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#include <zephyr/linker/sections.h>
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#include <zephyr/irq.h>
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/* UART registers struct */
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struct uart_cmsdk_apb {
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/* offset: 0x000 (r/w) data register */
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volatile uint32_t data;
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/* offset: 0x004 (r/w) status register */
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volatile uint32_t state;
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/* offset: 0x008 (r/w) control register */
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volatile uint32_t ctrl;
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union {
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/* offset: 0x00c (r/ ) interrupt status register */
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volatile uint32_t intstatus;
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/* offset: 0x00c ( /w) interrupt clear register */
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volatile uint32_t intclear;
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};
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/* offset: 0x010 (r/w) baudrate divider register */
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volatile uint32_t bauddiv;
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};
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/* UART Bits */
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/* CTRL Register */
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#define UART_TX_EN (1 << 0)
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#define UART_RX_EN (1 << 1)
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#define UART_TX_IN_EN (1 << 2)
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#define UART_RX_IN_EN (1 << 3)
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#define UART_TX_OV_EN (1 << 4)
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#define UART_RX_OV_EN (1 << 5)
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#define UART_HS_TM_TX (1 << 6)
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/* STATE Register */
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#define UART_TX_BF (1 << 0)
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#define UART_RX_BF (1 << 1)
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#define UART_TX_B_OV (1 << 2)
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#define UART_RX_B_OV (1 << 3)
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/* INTSTATUS Register */
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#define UART_TX_IN (1 << 0)
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#define UART_RX_IN (1 << 1)
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#define UART_TX_OV_IN (1 << 2)
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#define UART_RX_OV_IN (1 << 3)
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struct uart_cmsdk_apb_config {
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volatile struct uart_cmsdk_apb *uart;
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uint32_t sys_clk_freq;
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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uart_irq_config_func_t irq_config_func;
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#endif
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};
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/* Device data structure */
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struct uart_cmsdk_apb_dev_data {
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uint32_t baud_rate; /* Baud rate */
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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uart_irq_callback_user_data_t irq_cb;
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void *irq_cb_data;
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#endif
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/* UART Clock control in Active State */
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const struct arm_clock_control_t uart_cc_as;
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/* UART Clock control in Sleep State */
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const struct arm_clock_control_t uart_cc_ss;
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/* UART Clock control in Deep Sleep State */
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const struct arm_clock_control_t uart_cc_dss;
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};
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static const struct uart_driver_api uart_cmsdk_apb_driver_api;
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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static void uart_cmsdk_apb_isr(const struct device *dev);
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#endif
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/**
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* @brief Set the baud rate
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*
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* This routine set the given baud rate for the UART.
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*
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* @param dev UART device struct
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*/
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static void baudrate_set(const struct device *dev)
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{
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const struct uart_cmsdk_apb_config * const dev_cfg = dev->config;
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struct uart_cmsdk_apb_dev_data *const dev_data = dev->data;
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/*
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* If baudrate and/or sys_clk_freq are 0 the configuration remains
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* unchanged. It can be useful in case that Zephyr it is run via
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* a bootloader that brings up the serial and sets the baudrate.
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*/
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if ((dev_data->baud_rate != 0U) && (dev_cfg->sys_clk_freq != 0U)) {
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/* calculate baud rate divisor */
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dev_cfg->uart->bauddiv = (dev_cfg->sys_clk_freq / dev_data->baud_rate);
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}
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}
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/**
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* @brief Initialize UART channel
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*
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* This routine is called to reset the chip in a quiescent state.
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* It is assumed that this function is called only once per UART.
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*
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* @param dev UART device struct
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*
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* @return 0
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*/
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static int uart_cmsdk_apb_init(const struct device *dev)
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{
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const struct uart_cmsdk_apb_config * const dev_cfg = dev->config;
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#ifdef CONFIG_CLOCK_CONTROL
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/* Enable clock for subsystem */
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const struct device *const clk = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR_BY_IDX(0, 1));
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struct uart_cmsdk_apb_dev_data * const data = dev->data;
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if (!device_is_ready(clk)) {
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return -ENODEV;
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}
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#ifdef CONFIG_SOC_SERIES_BEETLE
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clock_control_on(clk, (clock_control_subsys_t) &data->uart_cc_as);
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clock_control_on(clk, (clock_control_subsys_t) &data->uart_cc_ss);
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clock_control_on(clk, (clock_control_subsys_t) &data->uart_cc_dss);
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#endif /* CONFIG_SOC_SERIES_BEETLE */
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#endif /* CONFIG_CLOCK_CONTROL */
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/* Set baud rate */
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baudrate_set(dev);
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/* Enable receiver and transmitter */
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dev_cfg->uart->ctrl = UART_RX_EN | UART_TX_EN;
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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dev_cfg->irq_config_func(dev);
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#endif
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return 0;
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}
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/**
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* @brief Poll the device for input.
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*
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* @param dev UART device struct
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* @param c Pointer to character
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*
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* @return 0 if a character arrived, -1 if the input buffer if empty.
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*/
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static int uart_cmsdk_apb_poll_in(const struct device *dev, unsigned char *c)
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{
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const struct uart_cmsdk_apb_config *dev_cfg = dev->config;
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/* If the receiver is not ready returns -1 */
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if (!(dev_cfg->uart->state & UART_RX_BF)) {
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return -1;
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}
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/* got a character */
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*c = (unsigned char)dev_cfg->uart->data;
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return 0;
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}
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/**
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* @brief Output a character in polled mode.
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*
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* Checks if the transmitter is empty. If empty, a character is written to
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* the data register.
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*
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* @param dev UART device struct
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* @param c Character to send
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*/
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static void uart_cmsdk_apb_poll_out(const struct device *dev,
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unsigned char c)
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{
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const struct uart_cmsdk_apb_config *dev_cfg = dev->config;
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/* Wait for transmitter to be ready */
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while (dev_cfg->uart->state & UART_TX_BF) {
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; /* Wait */
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}
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/* Send a character */
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dev_cfg->uart->data = (uint32_t)c;
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}
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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/**
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* @brief Fill FIFO with data
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*
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* @param dev UART device struct
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* @param tx_data Data to transmit
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* @param len Number of bytes to send
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*
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* @return the number of characters that have been read
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*/
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static int uart_cmsdk_apb_fifo_fill(const struct device *dev,
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const uint8_t *tx_data, int len)
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{
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const struct uart_cmsdk_apb_config *dev_cfg = dev->config;
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/*
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* No hardware FIFO present. Only 1 byte
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* to write if TX buffer is empty.
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*/
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if (len && !(dev_cfg->uart->state & UART_TX_BF)) {
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/*
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* Clear TX int. pending flag before pushing byte to "FIFO".
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* If TX interrupt is enabled the UART_TX_IN bit will be set
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* again automatically by the UART hardware machinery once
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* the "FIFO" becomes empty again.
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*/
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dev_cfg->uart->intclear = UART_TX_IN;
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dev_cfg->uart->data = *tx_data;
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return 1;
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}
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return 0;
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}
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/**
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* @brief Read data from FIFO
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*
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* @param dev UART device struct
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* @param rx_data Pointer to data container
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* @param size Container size in bytes
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*
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* @return the number of characters that have been read
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*/
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static int uart_cmsdk_apb_fifo_read(const struct device *dev,
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uint8_t *rx_data, const int size)
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{
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const struct uart_cmsdk_apb_config *dev_cfg = dev->config;
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/*
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* No hardware FIFO present. Only 1 byte
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* to read if RX buffer is full.
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*/
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if (size && dev_cfg->uart->state & UART_RX_BF) {
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/*
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* Clear RX int. pending flag before popping byte from "FIFO".
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* If RX interrupt is enabled the UART_RX_IN bit will be set
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* again automatically by the UART hardware machinery once
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* the "FIFO" becomes full again.
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*/
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dev_cfg->uart->intclear = UART_RX_IN;
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*rx_data = (unsigned char)dev_cfg->uart->data;
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return 1;
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}
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return 0;
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}
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/**
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* @brief Enable TX interrupt
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*
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* @param dev UART device struct
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*/
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static void uart_cmsdk_apb_irq_tx_enable(const struct device *dev)
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{
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const struct uart_cmsdk_apb_config *dev_cfg = dev->config;
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unsigned int key;
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dev_cfg->uart->ctrl |= UART_TX_IN_EN;
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/* The expectation is that TX is a level interrupt, active for as
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* long as TX buffer is empty. But in CMSDK UART it's an edge
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* interrupt, firing on a state change of TX buffer from full to
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* empty. So, we need to "prime" it here by calling ISR directly,
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* to get interrupt processing going, as there is no previous
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* full state to allow a transition from full to empty buffer
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* that will trigger a TX interrupt.
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*/
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key = irq_lock();
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uart_cmsdk_apb_isr(dev);
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irq_unlock(key);
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}
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/**
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* @brief Disable TX interrupt
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*
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* @param dev UART device struct
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*/
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static void uart_cmsdk_apb_irq_tx_disable(const struct device *dev)
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{
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const struct uart_cmsdk_apb_config *dev_cfg = dev->config;
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dev_cfg->uart->ctrl &= ~UART_TX_IN_EN;
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/* Clear any pending TX interrupt after disabling it */
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dev_cfg->uart->intclear = UART_TX_IN;
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}
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/**
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* @brief Verify if Tx interrupt has been raised
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*
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* @param dev UART device struct
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*
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* @return 1 if an interrupt is ready, 0 otherwise
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*/
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static int uart_cmsdk_apb_irq_tx_ready(const struct device *dev)
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{
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const struct uart_cmsdk_apb_config *dev_cfg = dev->config;
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return !(dev_cfg->uart->state & UART_TX_BF);
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}
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/**
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* @brief Enable RX interrupt
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*
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* @param dev UART device struct
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*/
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static void uart_cmsdk_apb_irq_rx_enable(const struct device *dev)
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{
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const struct uart_cmsdk_apb_config *dev_cfg = dev->config;
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dev_cfg->uart->ctrl |= UART_RX_IN_EN;
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}
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/**
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* @brief Disable RX interrupt
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*
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* @param dev UART device struct
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*/
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static void uart_cmsdk_apb_irq_rx_disable(const struct device *dev)
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{
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const struct uart_cmsdk_apb_config *dev_cfg = dev->config;
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dev_cfg->uart->ctrl &= ~UART_RX_IN_EN;
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/* Clear any pending RX interrupt after disabling it */
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dev_cfg->uart->intclear = UART_RX_IN;
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}
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/**
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* @brief Verify if Tx complete interrupt has been raised
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*
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* @param dev UART device struct
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*
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* @return 1 if an interrupt is ready, 0 otherwise
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*/
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static int uart_cmsdk_apb_irq_tx_complete(const struct device *dev)
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{
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return uart_cmsdk_apb_irq_tx_ready(dev);
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}
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/**
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* @brief Verify if Rx interrupt has been raised
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*
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* @param dev UART device struct
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*
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* @return 1 if an interrupt is ready, 0 otherwise
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*/
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static int uart_cmsdk_apb_irq_rx_ready(const struct device *dev)
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{
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const struct uart_cmsdk_apb_config *dev_cfg = dev->config;
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return (dev_cfg->uart->state & UART_RX_BF) == UART_RX_BF;
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}
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/**
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* @brief Enable error interrupt
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*
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* @param dev UART device struct
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*/
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static void uart_cmsdk_apb_irq_err_enable(const struct device *dev)
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{
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ARG_UNUSED(dev);
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}
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/**
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* @brief Disable error interrupt
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*
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* @param dev UART device struct
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*/
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static void uart_cmsdk_apb_irq_err_disable(const struct device *dev)
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{
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ARG_UNUSED(dev);
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}
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/**
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* @brief Verify if Tx or Rx interrupt is pending
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*
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* @param dev UART device struct
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*
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* @return 1 if Tx or Rx interrupt is pending, 0 otherwise
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*/
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static int uart_cmsdk_apb_irq_is_pending(const struct device *dev)
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{
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const struct uart_cmsdk_apb_config *dev_cfg = dev->config;
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return (dev_cfg->uart->intstatus & (UART_RX_IN | UART_TX_IN));
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}
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/**
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* @brief Update the interrupt status
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*
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* @param dev UART device struct
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*
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* @return always 1
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*/
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static int uart_cmsdk_apb_irq_update(const struct device *dev)
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{
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return 1;
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}
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/**
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* @brief Set the callback function pointer for an Interrupt.
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*
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* @param dev UART device structure
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* @param cb Callback function pointer.
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*/
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static void uart_cmsdk_apb_irq_callback_set(const struct device *dev,
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uart_irq_callback_user_data_t cb,
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void *cb_data)
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{
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struct uart_cmsdk_apb_dev_data *data = dev->data;
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data->irq_cb = cb;
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data->irq_cb_data = cb_data;
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}
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/**
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* @brief Interrupt service routine.
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*
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* Calls the callback function, if exists.
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*
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* @param arg argument to interrupt service routine.
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*/
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void uart_cmsdk_apb_isr(const struct device *dev)
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{
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struct uart_cmsdk_apb_dev_data *data = dev->data;
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/* Verify if the callback has been registered */
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if (data->irq_cb) {
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data->irq_cb(dev, data->irq_cb_data);
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}
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}
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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static const struct uart_driver_api uart_cmsdk_apb_driver_api = {
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.poll_in = uart_cmsdk_apb_poll_in,
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.poll_out = uart_cmsdk_apb_poll_out,
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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.fifo_fill = uart_cmsdk_apb_fifo_fill,
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.fifo_read = uart_cmsdk_apb_fifo_read,
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.irq_tx_enable = uart_cmsdk_apb_irq_tx_enable,
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.irq_tx_disable = uart_cmsdk_apb_irq_tx_disable,
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.irq_tx_ready = uart_cmsdk_apb_irq_tx_ready,
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.irq_rx_enable = uart_cmsdk_apb_irq_rx_enable,
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.irq_rx_disable = uart_cmsdk_apb_irq_rx_disable,
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.irq_tx_complete = uart_cmsdk_apb_irq_tx_complete,
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.irq_rx_ready = uart_cmsdk_apb_irq_rx_ready,
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.irq_err_enable = uart_cmsdk_apb_irq_err_enable,
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.irq_err_disable = uart_cmsdk_apb_irq_err_disable,
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.irq_is_pending = uart_cmsdk_apb_irq_is_pending,
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.irq_update = uart_cmsdk_apb_irq_update,
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.irq_callback_set = uart_cmsdk_apb_irq_callback_set,
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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};
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#if DT_NODE_HAS_STATUS(DT_DRV_INST(0), okay)
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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static void uart_cmsdk_apb_irq_config_func_0(const struct device *dev);
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#endif
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static const struct uart_cmsdk_apb_config uart_cmsdk_apb_dev_cfg_0 = {
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.uart = (volatile struct uart_cmsdk_apb *)DT_INST_REG_ADDR(0),
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.sys_clk_freq = DT_INST_PROP_BY_PHANDLE(0, clocks, clock_frequency),
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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.irq_config_func = uart_cmsdk_apb_irq_config_func_0,
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#endif
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};
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static struct uart_cmsdk_apb_dev_data uart_cmsdk_apb_dev_data_0 = {
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.baud_rate = DT_INST_PROP(0, current_speed),
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.uart_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE,
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.device = DT_INST_REG_ADDR(0),},
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.uart_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP,
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.device = DT_INST_REG_ADDR(0),},
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.uart_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP,
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.device = DT_INST_REG_ADDR(0),},
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};
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DEVICE_DT_INST_DEFINE(0,
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&uart_cmsdk_apb_init,
|
|
NULL,
|
|
&uart_cmsdk_apb_dev_data_0,
|
|
&uart_cmsdk_apb_dev_cfg_0, PRE_KERNEL_1,
|
|
CONFIG_SERIAL_INIT_PRIORITY,
|
|
&uart_cmsdk_apb_driver_api);
|
|
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
|
#if DT_NUM_IRQS(DT_DRV_INST(0)) == 1
|
|
static void uart_cmsdk_apb_irq_config_func_0(const struct device *dev)
|
|
{
|
|
IRQ_CONNECT(DT_INST_IRQN(0),
|
|
DT_INST_IRQ(0, priority),
|
|
uart_cmsdk_apb_isr,
|
|
DEVICE_DT_INST_GET(0),
|
|
0);
|
|
irq_enable(DT_INST_IRQN(0));
|
|
}
|
|
#else
|
|
static void uart_cmsdk_apb_irq_config_func_0(const struct device *dev)
|
|
{
|
|
IRQ_CONNECT(DT_INST_IRQ_BY_NAME(0, tx, irq),
|
|
DT_INST_IRQ_BY_NAME(0, tx, priority),
|
|
uart_cmsdk_apb_isr,
|
|
DEVICE_DT_INST_GET(0),
|
|
0);
|
|
irq_enable(DT_INST_IRQ_BY_NAME(0, tx, irq));
|
|
|
|
IRQ_CONNECT(DT_INST_IRQ_BY_NAME(0, rx, irq),
|
|
DT_INST_IRQ_BY_NAME(0, rx, priority),
|
|
uart_cmsdk_apb_isr,
|
|
DEVICE_DT_INST_GET(0),
|
|
0);
|
|
irq_enable(DT_INST_IRQ_BY_NAME(0, rx, irq));
|
|
}
|
|
#endif
|
|
#endif
|
|
|
|
#endif /* DT_NODE_HAS_STATUS(DT_DRV_INST(0), okay) */
|
|
|
|
#if DT_NODE_HAS_STATUS(DT_DRV_INST(1), okay)
|
|
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
|
static void uart_cmsdk_apb_irq_config_func_1(const struct device *dev);
|
|
#endif
|
|
|
|
static const struct uart_cmsdk_apb_config uart_cmsdk_apb_dev_cfg_1 = {
|
|
.uart = (volatile struct uart_cmsdk_apb *)DT_INST_REG_ADDR(1),
|
|
.sys_clk_freq = DT_INST_PROP_BY_PHANDLE(1, clocks, clock_frequency),
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
|
.irq_config_func = uart_cmsdk_apb_irq_config_func_1,
|
|
#endif
|
|
};
|
|
|
|
static struct uart_cmsdk_apb_dev_data uart_cmsdk_apb_dev_data_1 = {
|
|
.baud_rate = DT_INST_PROP(1, current_speed),
|
|
.uart_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE,
|
|
.device = DT_INST_REG_ADDR(1),},
|
|
.uart_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP,
|
|
.device = DT_INST_REG_ADDR(1),},
|
|
.uart_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP,
|
|
.device = DT_INST_REG_ADDR(1),},
|
|
};
|
|
|
|
DEVICE_DT_INST_DEFINE(1,
|
|
&uart_cmsdk_apb_init,
|
|
NULL,
|
|
&uart_cmsdk_apb_dev_data_1,
|
|
&uart_cmsdk_apb_dev_cfg_1, PRE_KERNEL_1,
|
|
CONFIG_SERIAL_INIT_PRIORITY,
|
|
&uart_cmsdk_apb_driver_api);
|
|
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
|
#if DT_NUM_IRQS(DT_DRV_INST(1)) == 1
|
|
static void uart_cmsdk_apb_irq_config_func_1(const struct device *dev)
|
|
{
|
|
IRQ_CONNECT(DT_INST_IRQN(1),
|
|
DT_INST_IRQ(1, priority),
|
|
uart_cmsdk_apb_isr,
|
|
DEVICE_DT_INST_GET(1),
|
|
0);
|
|
irq_enable(DT_INST_IRQN(1));
|
|
}
|
|
#else
|
|
static void uart_cmsdk_apb_irq_config_func_1(const struct device *dev)
|
|
{
|
|
IRQ_CONNECT(DT_INST_IRQ_BY_NAME(1, tx, irq),
|
|
DT_INST_IRQ_BY_NAME(1, tx, priority),
|
|
uart_cmsdk_apb_isr,
|
|
DEVICE_DT_INST_GET(1),
|
|
0);
|
|
irq_enable(DT_INST_IRQ_BY_NAME(1, tx, irq));
|
|
|
|
IRQ_CONNECT(DT_INST_IRQ_BY_NAME(1, rx, irq),
|
|
DT_INST_IRQ_BY_NAME(1, rx, priority),
|
|
uart_cmsdk_apb_isr,
|
|
DEVICE_DT_INST_GET(1),
|
|
0);
|
|
irq_enable(DT_INST_IRQ_BY_NAME(1, rx, irq));
|
|
}
|
|
#endif
|
|
#endif
|
|
|
|
#endif /* DT_NODE_HAS_STATUS(DT_DRV_INST(1), okay) */
|
|
|
|
#if DT_NODE_HAS_STATUS(DT_DRV_INST(2), okay)
|
|
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
|
static void uart_cmsdk_apb_irq_config_func_2(const struct device *dev);
|
|
#endif
|
|
|
|
static const struct uart_cmsdk_apb_config uart_cmsdk_apb_dev_cfg_2 = {
|
|
.uart = (volatile struct uart_cmsdk_apb *)DT_INST_REG_ADDR(2),
|
|
.sys_clk_freq = DT_INST_PROP_BY_PHANDLE(2, clocks, clock_frequency),
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
|
.irq_config_func = uart_cmsdk_apb_irq_config_func_2,
|
|
#endif
|
|
};
|
|
|
|
static struct uart_cmsdk_apb_dev_data uart_cmsdk_apb_dev_data_2 = {
|
|
.baud_rate = DT_INST_PROP(2, current_speed),
|
|
.uart_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE,
|
|
.device = DT_INST_REG_ADDR(2),},
|
|
.uart_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP,
|
|
.device = DT_INST_REG_ADDR(2),},
|
|
.uart_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP,
|
|
.device = DT_INST_REG_ADDR(2),},
|
|
};
|
|
|
|
DEVICE_DT_INST_DEFINE(2,
|
|
&uart_cmsdk_apb_init,
|
|
NULL,
|
|
&uart_cmsdk_apb_dev_data_2,
|
|
&uart_cmsdk_apb_dev_cfg_2, PRE_KERNEL_1,
|
|
CONFIG_SERIAL_INIT_PRIORITY,
|
|
&uart_cmsdk_apb_driver_api);
|
|
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
|
#if DT_NUM_IRQS(DT_DRV_INST(2)) == 1
|
|
static void uart_cmsdk_apb_irq_config_func_2(const struct device *dev)
|
|
{
|
|
IRQ_CONNECT(DT_INST_IRQN(2),
|
|
DT_INST_IRQ_BY_NAME(2, priority, irq),
|
|
uart_cmsdk_apb_isr,
|
|
DEVICE_DT_INST_GET(2),
|
|
0);
|
|
irq_enable(DT_INST_IRQN(2));
|
|
}
|
|
#else
|
|
static void uart_cmsdk_apb_irq_config_func_2(const struct device *dev)
|
|
{
|
|
IRQ_CONNECT(DT_INST_IRQ_BY_NAME(2, tx, irq),
|
|
DT_INST_IRQ_BY_NAME(2, tx, priority),
|
|
uart_cmsdk_apb_isr,
|
|
DEVICE_DT_INST_GET(2),
|
|
0);
|
|
irq_enable(DT_INST_IRQ_BY_NAME(2, tx, irq));
|
|
|
|
IRQ_CONNECT(DT_INST_IRQ_BY_NAME(2, rx, irq),
|
|
DT_INST_IRQ_BY_NAME(2, rx, priority),
|
|
uart_cmsdk_apb_isr,
|
|
DEVICE_DT_INST_GET(2),
|
|
0);
|
|
irq_enable(DT_INST_IRQ_BY_NAME(2, rx, irq));
|
|
}
|
|
#endif
|
|
#endif
|
|
|
|
#endif /* DT_NODE_HAS_STATUS(DT_DRV_INST(2), okay) */
|
|
|
|
#if DT_NODE_HAS_STATUS(DT_DRV_INST(3), okay)
|
|
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
|
static void uart_cmsdk_apb_irq_config_func_3(const struct device *dev);
|
|
#endif
|
|
|
|
static const struct uart_cmsdk_apb_config uart_cmsdk_apb_dev_cfg_3 = {
|
|
.uart = (volatile struct uart_cmsdk_apb *)DT_INST_REG_ADDR(3),
|
|
.sys_clk_freq = DT_INST_PROP_BY_PHANDLE(3, clocks, clock_frequency),
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
|
.irq_config_func = uart_cmsdk_apb_irq_config_func_3,
|
|
#endif
|
|
};
|
|
|
|
static struct uart_cmsdk_apb_dev_data uart_cmsdk_apb_dev_data_3 = {
|
|
.baud_rate = DT_INST_PROP(3, current_speed),
|
|
.uart_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE,
|
|
.device = DT_INST_REG_ADDR(3),},
|
|
.uart_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP,
|
|
.device = DT_INST_REG_ADDR(3),},
|
|
.uart_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP,
|
|
.device = DT_INST_REG_ADDR(3),},
|
|
};
|
|
|
|
DEVICE_DT_INST_DEFINE(3,
|
|
&uart_cmsdk_apb_init,
|
|
NULL,
|
|
&uart_cmsdk_apb_dev_data_3,
|
|
&uart_cmsdk_apb_dev_cfg_3, PRE_KERNEL_1,
|
|
CONFIG_SERIAL_INIT_PRIORITY,
|
|
&uart_cmsdk_apb_driver_api);
|
|
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
|
#if DT_NUM_IRQS(DT_DRV_INST(3)) == 1
|
|
static void uart_cmsdk_apb_irq_config_func_3(const struct device *dev)
|
|
{
|
|
IRQ_CONNECT(DT_INST_IRQN(3),
|
|
DT_INST_IRQ(3, priority),
|
|
uart_cmsdk_apb_isr,
|
|
DEVICE_DT_INST_GET(3),
|
|
0);
|
|
irq_enable(DT_INST_IRQN(3));
|
|
}
|
|
#else
|
|
static void uart_cmsdk_apb_irq_config_func_3(const struct device *dev)
|
|
{
|
|
IRQ_CONNECT(DT_INST_IRQ_BY_NAME(3, tx, irq),
|
|
DT_INST_IRQ_BY_NAME(3, tx, priority),
|
|
uart_cmsdk_apb_isr,
|
|
DEVICE_DT_INST_GET(3),
|
|
0);
|
|
irq_enable(DT_INST_IRQ_BY_NAME(3, tx, irq));
|
|
|
|
IRQ_CONNECT(DT_INST_IRQ_BY_NAME(3, rx, irq),
|
|
DT_INST_IRQ_BY_NAME(3, rx, priority),
|
|
uart_cmsdk_apb_isr,
|
|
DEVICE_DT_INST_GET(3),
|
|
0);
|
|
irq_enable(DT_INST_IRQ_BY_NAME(3, rx, irq));
|
|
}
|
|
#endif
|
|
#endif
|
|
|
|
#endif /* DT_NODE_HAS_STATUS(DT_DRV_INST(3), okay) */
|
|
|
|
#if DT_NODE_HAS_STATUS(DT_DRV_INST(4), okay)
|
|
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
|
static void uart_cmsdk_apb_irq_config_func_4(const struct device *dev);
|
|
#endif
|
|
|
|
static const struct uart_cmsdk_apb_config uart_cmsdk_apb_dev_cfg_4 = {
|
|
.uart = (volatile struct uart_cmsdk_apb *)DT_INST_REG_ADDR(4),
|
|
.sys_clk_freq = DT_INST_PROP_BY_PHANDLE(4, clocks, clock_frequency),
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
|
.irq_config_func = uart_cmsdk_apb_irq_config_func_4,
|
|
#endif
|
|
};
|
|
|
|
static struct uart_cmsdk_apb_dev_data uart_cmsdk_apb_dev_data_4 = {
|
|
.baud_rate = DT_INST_PROP(4, current_speed),
|
|
.uart_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE,
|
|
.device = DT_INST_REG_ADDR(4),},
|
|
.uart_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP,
|
|
.device = DT_INST_REG_ADDR(4),},
|
|
.uart_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP,
|
|
.device = DT_INST_REG_ADDR(4),},
|
|
};
|
|
|
|
DEVICE_DT_INST_DEFINE(4,
|
|
&uart_cmsdk_apb_init,
|
|
NULL,
|
|
&uart_cmsdk_apb_dev_data_4,
|
|
&uart_cmsdk_apb_dev_cfg_4, PRE_KERNEL_1,
|
|
CONFIG_SERIAL_INIT_PRIORITY,
|
|
&uart_cmsdk_apb_driver_api);
|
|
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
|
#if DT_NUM_IRQS(DT_DRV_INST(4)) == 1
|
|
static void uart_cmsdk_apb_irq_config_func_4(const struct device *dev)
|
|
{
|
|
IRQ_CONNECT(DT_INST_IRQN(4),
|
|
DT_INST_IRQ_BY_NAME(4, priority, irq),
|
|
uart_cmsdk_apb_isr,
|
|
DEVICE_DT_INST_GET(4),
|
|
0);
|
|
irq_enable(DT_INST_IRQN(4));
|
|
}
|
|
#else
|
|
static void uart_cmsdk_apb_irq_config_func_4(const struct device *dev)
|
|
{
|
|
IRQ_CONNECT(DT_INST_IRQ_BY_NAME(4, tx, irq),
|
|
DT_INST_IRQ_BY_NAME(4, tx, priority),
|
|
uart_cmsdk_apb_isr,
|
|
DEVICE_DT_INST_GET(4),
|
|
0);
|
|
irq_enable(DT_INST_IRQ_BY_NAME(4, tx, irq));
|
|
|
|
IRQ_CONNECT(DT_INST_IRQ_BY_NAME(4, rx, irq),
|
|
DT_INST_IRQ_BY_NAME(4, rx, priority),
|
|
uart_cmsdk_apb_isr,
|
|
DEVICE_DT_INST_GET(4),
|
|
0);
|
|
irq_enable(DT_INST_IRQ_BY_NAME(4, rx, irq));
|
|
}
|
|
#endif
|
|
#endif
|
|
|
|
#endif /* DT_NODE_HAS_STATUS(DT_DRV_INST(4), okay) */
|