68 lines
2.0 KiB
C
68 lines
2.0 KiB
C
/*
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* Copyright (c) 2020 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_IPM_IPM_CAVS_IDC_H_
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#define ZEPHYR_DRIVERS_IPM_IPM_CAVS_IDC_H_
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/* Redeclaration of the earlier IDC register API for platforms being
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* held back on this driver.
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*/
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#ifndef CONFIG_SOC_INTEL_S1000
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# ifndef IPC_DSP_BASE
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# define IPC_DSP_BASE(core) (DT_REG_ADDR(DT_NODELABEL(idc)) + 0x80 * (core))
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# endif
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#define IPC_IDCTFC(x) (x * 0x10)
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#define IPC_IDCTFC_BUSY BIT(31)
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#define IPC_IDCTFC_MSG_MASK 0x7FFFFFFF
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#define IPC_IDCTEFC(x) (0x4 + x * 0x10)
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#define IPC_IDCTEFC_MSG_MASK 0x3FFFFFFF
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#define IPC_IDCITC(x) (0x8 + x * 0x10)
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#define IPC_IDCITC_MSG_MASK 0x7FFFFFFF
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#define IPC_IDCITC_BUSY BIT(31)
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#define IPC_IDCIETC(x) (0xc + x * 0x10)
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#define IPC_IDCIETC_MSG_MASK 0x3FFFFFFF
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#define IPC_IDCIETC_DONE BIT(30)
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#define IPC_IDCCTL 0x50
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#define IPC_IDCCTL_IDCTBIE(x) BIT(x)
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#endif
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#define IPM_CAVS_IDC_ID_MASK \
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(CAVS_IDC_TYPE(CAVS_IDC_TYPE_MASK) | \
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CAVS_IDC_HEADER(CAVS_IDC_HEADER_MASK))
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/* IDC message type. */
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#define CAVS_IDC_TYPE_SHIFT 24U
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#define CAVS_IDC_TYPE_MASK 0x7FU
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#define CAVS_IDC_TYPE(x) \
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(((x) & CAVS_IDC_TYPE_MASK) << CAVS_IDC_TYPE_SHIFT)
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/* IDC message header. */
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#define CAVS_IDC_HEADER_MASK 0xFFFFFFU
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#define CAVS_IDC_HEADER(x) ((x) & CAVS_IDC_HEADER_MASK)
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/* IDC message extension. */
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#define CAVS_IDC_EXTENSION_MASK 0x3FFFFFFFU
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#define CAVS_IDC_EXTENSION(x) ((x) & CAVS_IDC_EXTENSION_MASK)
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/* Scheduler IPI message (type 0x7F, header 'IPI' in ascii) */
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#define IPM_CAVS_IDC_MSG_SCHED_IPI_DATA 0
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#define IPM_CAVS_IDC_MSG_SCHED_IPI_ID \
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(CAVS_IDC_TYPE(0x7FU) | CAVS_IDC_HEADER(0x495049U))
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static inline uint32_t idc_read(uint32_t reg, uint32_t core_id)
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{
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return *((volatile uint32_t*)(IPC_DSP_BASE(core_id) + reg));
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}
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static inline void idc_write(uint32_t reg, uint32_t core_id, uint32_t val)
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{
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*((volatile uint32_t*)(IPC_DSP_BASE(core_id) + reg)) = val;
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}
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int cavs_idc_smp_init(const struct device *dev);
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#endif /* ZEPHYR_DRIVERS_IPM_IPM_CAVS_IDC_H_ */
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