294 lines
9.9 KiB
ReStructuredText
294 lines
9.9 KiB
ReStructuredText
.. _Intel_S1000:
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Intel S1000 CRB
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###############
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Overview
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********
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The Intel S1000 ASIC is designed for complex far-field signal processing
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algorithms that use high dimensional microphone arrays to do beamforming,
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cancel echoes, and reduce noise. It connects to a host processor chip via
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simple SPI and I2S interfaces, to the microphone array via I2S or PDM
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interfaces, and to speakers via I2S. In addition, it has an I2C interface
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for controlling platform components such as ADCs, DACs, CODECs and PMICs.
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.. image:: ./intel_s1000_crb.png
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:width: 442px
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:align: center
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:alt: Intel Speech Enabling Developer Kit
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The Intel S1000 contains the following:
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- Dual DSP
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- Dual 400 MHz Tensilica HiFi3 cores
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- Single precision scalar floating-point
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- 16KB 4-way I$; 48KB 4-way D$
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- Inference Engine
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- On-chip Neural Network Accelerator
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- Internal Memory
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- 4MB shared embedded SRAM
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- 64KB embedded SRAM for streaming samples in low power mode
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- External Memory Interfaces
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- Up to 8MB external 16-bit PSRAM
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- Up to 128MB external SPI flash
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- I/O Interfaces
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- Host I/O: SPI or USB 2.0 High-speed device
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- Microphone: I2S/TDM 9.6 MHz max. bit clock
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- Digital Microphone: 4 stereo PDM ports up to 4.8 MHz clock
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- Speaker: I2S/TDM 9.6 MHz max. bit clock
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- Instrumentation: I2C master @ 100/400 KHz
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- Debug: UART up to 2.4 Mbaud/s
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- GPIO: 8 GPIOs with PWM output capability
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.. note::
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This board is not available for purchase anymore.
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System requirements
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*******************
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Prerequisites
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=============
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The Xtensa 'toolchain' i.e. XCC is required to build this port. This needs a
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license and is available for Linux and Windows from Cadence.
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In order to download the installer and the core configuration, users need to
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have a registered account at https://tensilicatools.com.
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The toolchain installer and the core configuration can be downloaded by following
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the links at `Tensilica Tools for Sue Creek`_
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Select version RI-2018.0 and download the archive. The archive contains two files:
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- Installer: :file:`Xplorer-8.0.8-linux-x64-installer.bin` and
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- Core configuration
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:file:`X6H3SUE_RI_2018_0_linux_redist.tgz`
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For JTAG based debugging, download the XOCD package as well.
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A node locked license key can also be generated from the `SDK portal`_.
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.. note::
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Please upgrade to RI-2018.0 version of XCC if you have previously installed
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the older RF-2016.4 version of XCC. The old toolchain does not support
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the C/C++ standards required for building Zephyr applications.
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Set up build environment
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========================
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Run the installer using these commands:
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.. code-block:: console
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cd ~/Downloads
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chmod +x Xplorer-8.0.8-linux-installer.bin
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./Xplorer-8.0.8-linux-installer.bin
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Please note a dialogue box should pop-up after running this command. In case the
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graphical installation tool does not start, the tool will revert to console
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based installation. The graphical tool is the preferred installation method.
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If the graphical tool does not start, it means your system is missing some
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packages which is preventing successful installation, most probably
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``gtk2-i686``. You can install any missing packages with::
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sudo apt-get install gtk2-i686
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On Fedora 29 you might need to install the following packages::
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sudo dnf install libXtst.i686 libnsl.i686 gtk2.i686
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.. note::
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The SDK is a 32 bit binary, so you will need to install 32bit compatibility
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packages for this work.
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Follow the instructions and install the toolchain and related tools in your
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preferred path.
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After a successful installation of the tool, run the Xtensa Xplorer (it will run
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automatically after installation is done) and follow the steps to install the
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software keys you have downloaded from `Tensilica Tools for Sue Creek`_
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.. note::
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The license key you have requested is tied to the Ethernet MAC address on the
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host system. The license manager expects a network device named ``eth0`` or
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``eth1``. On many modern Linux distribution the naming scheme is different
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and determined automatically. You will need to either force the naming to
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follow what the license manager expects or create a dedicated ethernet device
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for this to work.
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On Ubuntu 18.04 LTS, you can install the license key manually with
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.. code-block:: console
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cp sue-creek-SDK-license.dat <path to SDK>/XtDevTools/install/tools/RI-2018.0-linux/XtensaTools/Tools/lic/license.dat"
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After the tool chain is successfully installed, the core build needs to be
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installed as follows
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.. code-block:: console
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tar -xvzf X6H3SUE_RI_2018_0_linux_redist.tgz --directory <path to SDK>/XtDevTools/install/builds
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cd <path to SDK>/XtDevTools/install/builds/RI-2018.0-linux/X6H3SUE_RI_2018_0
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./install
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The :file:`install` script is the Xtensa Processor Configuration Installation
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Tool which is required to update the installation path. When it prompts to
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enter the path to the Xtensa Tools directory, enter
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:file:`<path to SDK>/XtDevTools/install/tools/RI-2018.0-linux/XtensaTools`.
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You should use the default registry
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:file:`<path to SDK>/XtDevTools/install/tools/RI-2018.0-linux/XtensaTools/config`.
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With the XCC toolchain installed, the Zephyr build system must be instructed
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to use this particular variant by setting the ``ZEPHYR_TOOLCHAIN_VARIANT``
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shell variable. Some more environment variables are also required (see below):
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.. code-block:: console
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export XTENSA_TOOLCHAIN_PATH=<path to SDK>
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export ZEPHYR_TOOLCHAIN_VARIANT=xcc
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export TOOLCHAIN_VER=RI-2018.0-linux
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export XTENSA_CORE=X6H3SUE_RI_2018_0
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export XTENSA_SYSTEM=${XTENSA_TOOLCHAIN_PATH}/XtDevTools/install/tools/RI-2018.0-linux/XtensaTools/config/
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export XTENSA_BUILD_PATHS=${XTENSA_TOOLCHAIN_PATH}/XtDevTools/install/builds/
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export XTENSA_OCD_PATH=<path to XOCD>/xocd-12.0.4
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Programming and Debugging
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*************************
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Flashing
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========
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The usual ``flash`` target will work with the ``intel_s1000_crb`` board
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configuration using JTAG. Here is an example for the :ref:`hello_world`
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application.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: intel_s1000_crb
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:goals: flash
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Refer to :ref:`build_an_application` and :ref:`application_run` for
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more details.
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Downloading binary image
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========================
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A Linux host connected to the SPI interface of the ``intel_s1000_crb`` board
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can download a zephyr binary to RAM and execute the image.
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.. code-block:: console
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cd <app-dir>/build
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sudo -E python3 \
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$ZEPHYR_BASE/boards/xtensa/intel_s1000_crb/support/download.py \
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zephyr/zephyr.bin
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The script depends on a few python modules. These dependencies can be installed
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on the Linux host using the command below.
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.. code-block:: console
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pip3 install --user pyyaml python-periphery hashlib bitstruct
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Setting up UART
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===============
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We recommend using a "FT232RL FTDI USB To TTL Serial Converter Adapter Module"
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to tap the UART data. The J8 Header on S1000 CRB is dedicated for UART.
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Connect the J8 header and UART chip as shown below:
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+------------+-----------+
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| UART chip | J8 Header |
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+============+===========+
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| DTR | |
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+------------+-----------+
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| RX | 2 |
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+------------+-----------+
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| TX | 4 |
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+------------+-----------+
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| VCC | |
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+------------+-----------+
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| CTS | |
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+------------+-----------+
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| GND | 10 |
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+------------+-----------+
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Attach one end of the USB cable to the UART chip and the other end to the
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Linux system. Use ``minicom`` or another terminal emulator to monitor the
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UART data by following these steps:
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.. code-block:: console
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dmesg | grep USB
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minicom -D /dev/ttyUSB0
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Here, the first command will indicate the tty to which the USB is connected.
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The second command assumes it was USB0 and opens up minicom. You can suitably
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modify the second command based on the output of the first command. The serial
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settings configured in zephyr is "115200 8N1". This is also the default
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settings in minicom and can be verified by pressing Ctrl-A Z P.
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Using JTAG
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==========
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For debugging and flashing, you can use a flyswatter2 to connect to the Intel
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S1000 CRB.
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The pinouts for flyswatter2 and the corresponding pinouts for CRB are
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shown below. Note that pin 6 on CRB is left unconnected.
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The corresponding pin mapping is
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+-----------+-------------+-------------+-----------+
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| S1000 | Flyswatter2 | Flyswatter2 | S1000 |
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+===========+=============+=============+===========+
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| 7 | 1 | 11 | NC |
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+-----------+-------------+-------------+-----------+
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| NC | 2 | 12 | NC |
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+-----------+-------------+-------------+-----------+
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| 4 | 3 | 13 | 5 |
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+-----------+-------------+-------------+-----------+
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| NC | 4 | 14 | NC |
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+-----------+-------------+-------------+-----------+
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| 3 | 5 | 15 | NC |
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+-----------+-------------+-------------+-----------+
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| 8 | 6 | 16 | NC |
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+-----------+-------------+-------------+-----------+
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| 2 | 7 | 17 | NC |
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+-----------+-------------+-------------+-----------+
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| NC | 8 | 18 | NC |
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+-----------+-------------+-------------+-----------+
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| 1 | 9 | 19 | NC |
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+-----------+-------------+-------------+-----------+
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| NC | 10 | 20 | NC |
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+-----------+-------------+-------------+-----------+
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Ideally, these connections should have been enough to get the debug working.
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However, we need to short 2 pins on Host Connector J3 via a 3.3k resistor
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(simple shorting without the resistor will also do) for debugging to work.
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Those 2 pins are Pin5 HOST_RST_N_LT_R) and Pin21 (+V_HOST_3P3_1P8).
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.. target-notes::
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.. _`FT232 UART`: https://www.amazon.com/FT232RL-Serial-Converter-Adapter-Arduino/dp/B06XDH2VK9
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.. _Tensilica Tools for Sue Creek: https://tensilicatools.com/platform/intel-sue-creek
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.. _SDK portal: https://tensilicatools.com
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