48 lines
1.2 KiB
C
48 lines
1.2 KiB
C
/*
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* Copyright (c) 2016 Cadence Design Systems, Inc.
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/tracing/tracing.h>
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void arch_cpu_idle(void)
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{
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sys_trace_idle();
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/* Just spin forever with interrupts unmasked, for platforms
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* where WAITI can't be used or where its behavior is
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* complicated (Intel DSPs will power gate on idle entry under
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* some circumstances)
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*/
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if (IS_ENABLED(CONFIG_XTENSA_CPU_IDLE_SPIN)) {
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__asm__ volatile("rsil a0, 0");
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__asm__ volatile("loop_forever: j loop_forever");
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return;
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}
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/* Cribbed from SOF: workaround for a bug in some versions of
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* the LX6 IP. Preprocessor ugliness avoids the need to
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* figure out how to get the compiler to unroll a loop.
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*/
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if (IS_ENABLED(CONFIG_XTENSA_WAITI_BUG)) {
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#define NOP4 __asm__ volatile("nop; nop; nop; nop");
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#define NOP32 NOP4 NOP4 NOP4 NOP4 NOP4 NOP4 NOP4 NOP4
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#define NOP128() NOP32 NOP32 NOP32 NOP32
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NOP128();
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#undef NOP128
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#undef NOP32
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#undef NOP4
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__asm__ volatile("isync; extw");
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}
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__asm__ volatile ("waiti 0");
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}
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void arch_cpu_atomic_idle(unsigned int key)
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{
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sys_trace_idle();
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__asm__ volatile ("waiti 0\n\t"
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"wsr.ps %0\n\t"
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"rsync" :: "a"(key));
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}
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