Marek Matej 1c130d0060 arch: xtensa: Enable builds without the multithreading ... Allow builds which has CONFIG_MULTITHREADING disabled. This is reduce code footprint which is handy for constrained targets as bootloaders. Signed-off-by: Marek Matej <marek.matej@espressif.com>		2023-05-25 16:15:54 +02:00
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include	xtensa: mmu: Initial implementation	2023-05-23 08:54:29 +02:00
offsets	xtensa: add some structs for interrupt stack frames	2023-04-20 04:45:52 -04:00
startup	…
CMakeLists.txt	xtensa: mmu: Initial implementation	2023-05-23 08:54:29 +02:00
README-WINDOWS.rst	…
coredump.c	xtensa: add some structs for interrupt stack frames	2023-04-20 04:45:52 -04:00
cpu_idle.c	arch/xtensa: undefine NOP32	2023-05-25 04:49:14 -04:00
crt1.S	…
debug_helpers_asm.S	xtensa: add some structs for interrupt stack frames	2023-04-20 04:45:52 -04:00
fatal.c	xtensa: limit speical exit() to XT_SIMULATOR	2023-05-08 09:59:54 +02:00
gdbstub.c	xtensa: add some structs for interrupt stack frames	2023-04-20 04:45:52 -04:00
gen_zsr.py	xtensa: gen_zsr: add _STR for extra registers	2023-05-23 08:54:29 +02:00
irq_manage.c	…
irq_offload.c	…
timing.c	…
tls.c	…
window_vectors.S	…
xcc_stubs.c	…
xtensa-asm2-util.S	xtensa: mmu: handle TLB misses in C exception handler	2023-05-23 08:54:29 +02:00
xtensa-asm2.c	arch: xtensa: Enable builds without the multithreading	2023-05-25 16:15:54 +02:00
xtensa_backtrace.c	arch: xtensa: Remove unecessary logic in backtrace	2023-05-12 18:31:13 -04:00
xtensa_intgen.py	…
xtensa_intgen.tmpl	…
xtensa_mmu.c	xtensa: mmu: always map data TLB for VECBASE	2023-05-23 08:54:29 +02:00