122 lines
3.5 KiB
C
122 lines
3.5 KiB
C
/*
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* Copyright (c) 2017, Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_ARCH_XTENSA_INCLUDE_XTENSA_ASM2_CONTEXT_H_
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#define ZEPHYR_ARCH_XTENSA_INCLUDE_XTENSA_ASM2_CONTEXT_H_
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#include <xtensa/corebits.h>
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#include <xtensa/config/core-isa.h>
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/*
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* Stack frame layout for a saved processor context, in memory order,
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* high to low address:
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*
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* SP-0 <-- Interrupted stack pointer points here
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*
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* SP-4 Caller A3 spill slot \
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* SP-8 Caller A2 spill slot |
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* SP-12 Caller A1 spill slot + (Part of ABI standard)
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* SP-16 Caller A0 spill slot /
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*
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* SP-20 Saved A3
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* SP-24 Saved A2
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* SP-28 Unused (not "Saved A1" because the SP is saved externally as a handle)
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* SP-32 Saved A0
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*
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* SP-36 Saved PC (address to jump to following restore)
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* SP-40 Saved/interrupted PS special register
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*
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* SP-44 Saved SAR special register
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*
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* SP-48 Saved LBEG special register (if loops enabled)
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* SP-52 Saved LEND special register (if loops enabled)
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* SP-56 Saved LCOUNT special register (if loops enabled)
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*
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* SP-60 Saved SCOMPARE special register (if S32C1I enabled)
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*
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* (The above fixed-size region is known as the "base save area" in the
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* code below)
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*
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* - Saved A7 \
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* - Saved A6 |
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* - Saved A5 +- If not in-use by another frame
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* - Saved A4 /
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*
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* - Saved A11 \
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* - Saved A10 |
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* - Saved A9 +- If not in-use by another frame
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* - Saved A8 /
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*
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* - Saved A15 \
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* - Saved A14 |
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* - Saved A13 +- If not in-use by another frame
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* - Saved A12 /
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*
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* - Saved intermediate stack pointer (points to low word of base save
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* area, i.e. the saved LCOUNT or SAR). The pointer to this value
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* (i.e. the final stack pointer) is stored externally as the
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* "restore handle" in the thread context.
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*
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* Essentially, you can recover a pointer to the BSA by loading *SP.
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* Adding the fixed BSA size to that gets you back to the
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* original/interrupted stack pointer.
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*/
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#define BASE_SAVE_AREA_SIZE_COMMON 44
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#if XCHAL_HAVE_LOOPS
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#define BASE_SAVE_AREA_SIZE_LOOPS 12
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#else
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#define BASE_SAVE_AREA_SIZE_LOOPS 0
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#endif
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#if XCHAL_HAVE_S32C1I
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#define BASE_SAVE_AREA_SIZE_SCOMPARE 4
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#else
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#define BASE_SAVE_AREA_SIZE_SCOMPARE 0
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#endif
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#if XCHAL_HAVE_THREADPTR && defined(CONFIG_THREAD_LOCAL_STORAGE)
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#define BASE_SAVE_AREA_SIZE_THREADPTR 4
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#else
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#define BASE_SAVE_AREA_SIZE_THREADPTR 0
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#endif
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#define BASE_SAVE_AREA_SIZE \
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(BASE_SAVE_AREA_SIZE_COMMON + \
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BASE_SAVE_AREA_SIZE_LOOPS + \
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BASE_SAVE_AREA_SIZE_SCOMPARE + \
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BASE_SAVE_AREA_SIZE_THREADPTR)
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#define BSA_A3_OFF (BASE_SAVE_AREA_SIZE - 20)
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#define BSA_A2_OFF (BASE_SAVE_AREA_SIZE - 24)
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#define BSA_SCRATCH_OFF (BASE_SAVE_AREA_SIZE - 28)
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#define BSA_A0_OFF (BASE_SAVE_AREA_SIZE - 32)
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#define BSA_PC_OFF (BASE_SAVE_AREA_SIZE - 36)
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#define BSA_PS_OFF (BASE_SAVE_AREA_SIZE - 40)
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#define BSA_SAR_OFF (BASE_SAVE_AREA_SIZE - 44)
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#define BSA_LBEG_OFF (BASE_SAVE_AREA_SIZE - 48)
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#define BSA_LEND_OFF (BASE_SAVE_AREA_SIZE - 52)
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#define BSA_LCOUNT_OFF (BASE_SAVE_AREA_SIZE - 56)
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#if XCHAL_HAVE_S32C1I
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#define BSA_SCOMPARE1_OFF \
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(BASE_SAVE_AREA_SIZE - \
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(BASE_SAVE_AREA_SIZE_COMMON + \
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BASE_SAVE_AREA_SIZE_LOOPS + \
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BASE_SAVE_AREA_SIZE_SCOMPARE))
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#endif
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#if XCHAL_HAVE_THREADPTR && defined(CONFIG_THREAD_LOCAL_STORAGE)
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#define BSA_THREADPTR_OFF \
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(BASE_SAVE_AREA_SIZE - \
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(BASE_SAVE_AREA_SIZE_COMMON + \
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BASE_SAVE_AREA_SIZE_LOOPS + \
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BASE_SAVE_AREA_SIZE_SCOMPARE + \
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BASE_SAVE_AREA_SIZE_THREADPTR))
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#endif
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#endif /* ZEPHYR_ARCH_XTENSA_INCLUDE_XTENSA_ASM2_CONTEXT_H_ */
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