119 lines
3.8 KiB
C
119 lines
3.8 KiB
C
/*
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* Copyright (c) 2017, Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of the Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL CORPORATION OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "qm_common.h"
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#include "ss_clk.h"
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int ss_clk_gpio_enable(const qm_ss_gpio_t gpio)
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{
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QM_CHECK(gpio < QM_SS_GPIO_NUM, -EINVAL);
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int addr =
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(gpio == QM_SS_GPIO_0) ? QM_SS_GPIO_0_BASE : QM_SS_GPIO_1_BASE;
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__builtin_arc_sr(QM_SS_GPIO_LS_SYNC_CLK_EN |
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QM_SS_GPIO_LS_SYNC_SYNC_LVL,
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addr + QM_SS_GPIO_LS_SYNC);
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return 0;
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}
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int ss_clk_gpio_disable(const qm_ss_gpio_t gpio)
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{
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QM_CHECK(gpio < QM_SS_GPIO_NUM, -EINVAL);
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int addr =
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(gpio == QM_SS_GPIO_0) ? QM_SS_GPIO_0_BASE : QM_SS_GPIO_1_BASE;
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__builtin_arc_sr(0, addr + QM_SS_GPIO_LS_SYNC);
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return 0;
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}
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int ss_clk_spi_enable(const qm_ss_spi_t spi)
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{
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QM_CHECK(spi < QM_SS_SPI_NUM, -EINVAL);
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int addr = (spi == QM_SS_SPI_0) ? QM_SS_SPI_0_BASE : QM_SS_SPI_1_BASE;
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QM_SS_REG_AUX_OR(addr + QM_SS_SPI_CTRL, QM_SS_SPI_CTRL_CLK_ENA);
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return 0;
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}
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int ss_clk_spi_disable(const qm_ss_spi_t spi)
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{
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QM_CHECK(spi < QM_SS_SPI_NUM, -EINVAL);
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int addr = (spi == QM_SS_SPI_0) ? QM_SS_SPI_0_BASE : QM_SS_SPI_1_BASE;
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QM_SS_REG_AUX_NAND(addr + QM_SS_SPI_CTRL, QM_SS_SPI_CTRL_CLK_ENA);
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return 0;
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}
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int ss_clk_i2c_enable(const qm_ss_i2c_t i2c)
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{
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QM_CHECK(i2c < QM_SS_I2C_NUM, -EINVAL);
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int addr = (i2c == QM_SS_I2C_0) ? QM_SS_I2C_0_BASE : QM_SS_I2C_1_BASE;
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QM_SS_REG_AUX_OR(addr + QM_SS_I2C_CON, QM_SS_I2C_CON_CLK_ENA);
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return 0;
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}
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int ss_clk_i2c_disable(const qm_ss_i2c_t i2c)
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{
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QM_CHECK(i2c < QM_SS_I2C_NUM, -EINVAL);
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int addr = (i2c == QM_SS_I2C_0) ? QM_SS_I2C_0_BASE : QM_SS_I2C_1_BASE;
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QM_SS_REG_AUX_NAND(addr + QM_SS_I2C_CON, QM_SS_I2C_CON_CLK_ENA);
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return 0;
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}
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int ss_clk_adc_enable(void)
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{
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/* Enable the ADC clock */
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QM_SS_REG_AUX_OR(QM_SS_ADC_BASE + QM_SS_ADC_CTRL,
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QM_SS_ADC_CTRL_CLK_ENA);
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return 0;
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}
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int ss_clk_adc_disable(void)
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{
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/* Disable the ADC clock */
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QM_SS_REG_AUX_NAND(QM_SS_ADC_BASE + QM_SS_ADC_CTRL,
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QM_SS_ADC_CTRL_CLK_ENA);
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return 0;
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}
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int ss_clk_adc_set_div(const uint32_t div)
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{
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uint32_t reg;
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/*
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* Scale the max divisor with the system clock speed. Clock speeds less
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* than 1 MHz will not work properly.
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*/
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QM_CHECK(div <= QM_SS_ADC_DIV_MAX * clk_sys_get_ticks_per_us(),
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-EINVAL);
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/* Set the ADC divisor */
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reg = __builtin_arc_lr(QM_SS_ADC_BASE + QM_SS_ADC_DIVSEQSTAT);
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reg &= ~(QM_SS_ADC_DIVSEQSTAT_CLK_RATIO_MASK);
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__builtin_arc_sr(reg | div, QM_SS_ADC_BASE + QM_SS_ADC_DIVSEQSTAT);
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return 0;
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}
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