216 lines
3.9 KiB
Plaintext
216 lines
3.9 KiB
Plaintext
/*
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* Copyright (c) 2017 Google LLC.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <arm/armv6-m.dtsi>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/i2c/i2c.h>
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/ {
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aliases {
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watchdog0 = &wdog;
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};
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chosen {
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zephyr,flash-controller = &nvmctrl;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m0+";
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reg = <0>;
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};
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};
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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reg = <0x20000000 0x8000>;
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};
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id: device_id@80a00c {
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compatible = "atmel,sam0-id";
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reg = <0x0080A00C 0x4>,
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<0x0080A040 0x4>,
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<0x0080A044 0x4>,
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<0x0080A048 0x4>;
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};
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aliases {
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port-a = &porta;
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port-b = &portb;
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adc-0 = &adc;
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sercom-0 = &sercom0;
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sercom-1 = &sercom1;
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sercom-2 = &sercom2;
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sercom-3 = &sercom3;
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sercom-4 = &sercom4;
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sercom-5 = &sercom5;
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tc-4 = &tc4;
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};
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soc {
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nvmctrl: nvmctrl@41004000 {
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compatible = "atmel,sam0-nvmctrl";
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label = "FLASH_CTRL";
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reg = <0x41004000 0x22>;
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interrupts = <5 0>;
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lock-regions = <16>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@0 {
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compatible = "soc-nv-flash";
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label = "FLASH_0";
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reg = <0 0x40000>;
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write-block-size = <64>;
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};
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};
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pm: pm@40000400 {
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compatible = "atmel,samd2x-pm";
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reg = <0x40000400 0x400>;
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interrupts = <0 0>;
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#clock-cells = <2>;
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};
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gclk: gclk@40000c00 {
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compatible = "atmel,samd2x-gclk";
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reg = <0x40000c00 0x400>;
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#clock-cells = <1>;
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};
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eic: eic@40001800 {
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compatible = "atmel,sam0-eic";
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reg = <0x40001800 0x1C>;
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interrupts = <4 0>;
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label = "EIC";
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};
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pinmux_a: pinmux@41004400 {
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compatible = "atmel,sam0-pinmux";
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reg = <0x41004400 0x80>;
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};
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pinmux_b: pinmux@41004480 {
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compatible = "atmel,sam0-pinmux";
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reg = <0x41004480 0x80>;
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};
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wdog: watchdog@40001000 {
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compatible = "atmel,sam0-watchdog";
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reg = <0x40001000 9>;
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interrupts = <2 0>;
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label = "WATCHDOG_0";
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};
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sercom0: sercom@42000800 {
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compatible = "atmel,sam0-sercom";
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reg = <0x42000800 0x40>;
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status = "disabled";
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label = "SERCOM0";
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};
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sercom1: sercom@42000c00 {
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compatible = "atmel,sam0-sercom";
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reg = <0x42000c00 0x40>;
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status = "disabled";
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label = "SERCOM1";
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};
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sercom2: sercom@42001000 {
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compatible = "atmel,sam0-sercom";
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reg = <0x42001000 0x40>;
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status = "disabled";
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label = "SERCOM2";
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};
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sercom3: sercom@42001400 {
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compatible = "atmel,sam0-sercom";
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reg = <0x42001400 0x40>;
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status = "disabled";
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label = "SERCOM3";
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};
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sercom4: sercom@42001800 {
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compatible = "atmel,sam0-sercom";
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reg = <0x42001800 0x40>;
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status = "disabled";
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label = "SERCOM4";
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};
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sercom5: sercom@42001c00 {
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compatible = "atmel,sam0-sercom";
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reg = <0x42001c00 0x40>;
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status = "disabled";
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label = "SERCOM5";
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};
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tc4: tc@42003000 {
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compatible = "atmel,sam0-tc32";
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reg = <0x42003000 0x20>;
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label = "TIMER_4";
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};
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porta: gpio@41004400 {
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compatible = "atmel,sam0-gpio";
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reg = <0x41004400 0x80>;
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label = "PORTA";
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gpio-controller;
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#gpio-cells = <2>;
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};
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portb: gpio@41004480 {
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compatible = "atmel,sam0-gpio";
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reg = <0x41004480 0x80>;
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label = "PORTB";
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gpio-controller;
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#gpio-cells = <2>;
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};
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rtc: rtc@40001400 {
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compatible = "atmel,sam0-rtc";
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reg = <0x40001400 0x1C>;
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interrupts = <3 0>;
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clock-generator = <0>;
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status = "disabled";
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label = "RTC";
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};
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adc: adc@42004000 {
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compatible = "atmel,sam0-adc";
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reg = <0x42004000 0x2B>;
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label = "ADC_0";
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/*
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* 2.1 MHz max, so clock it with the
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* 8 MHz GCLK / 4 = 2 MHz
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*/
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gclk = <3>;
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prescaler = <4>;
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#io-channel-cells = <1>;
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};
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dac0: dac@42004800 {
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compatible = "atmel,sam0-dac";
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status = "disabled";
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reg = <0x42004800 0x10>;
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label = "DAC_0";
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#io-channel-cells = <0>;
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <2>;
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};
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