zephyr/soc/xtensa
Adrian Bonislawski 728506df6f soc: intel_adsp/ace: wait for lpsram power up
Wait for lpsram power up before bbzero

Fixes commit 195db14

Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
2022-11-08 10:48:30 +01:00
..
esp32 soc/xtensa: Use standard __data_start/__data_end markers 2022-11-03 10:25:07 +01:00
esp32_net soc/xtensa: Use standard __data_start/__data_end markers 2022-11-03 10:25:07 +01:00
esp32s2 soc/xtensa: Use standard __data_start/__data_end markers 2022-11-03 10:25:07 +01:00
intel_adsp soc: intel_adsp/ace: wait for lpsram power up 2022-11-08 10:48:30 +01:00
nxp_adsp soc/xtensa: Use standard __data_start/__data_end markers 2022-11-03 10:25:07 +01:00
sample_controller arch/xtensa: Enable code relocation 2022-11-03 10:25:07 +01:00
CMakeLists.txt soc/xtensa/intel_adsp: Upstream updates 2020-10-21 06:38:53 -04:00