157 lines
5.0 KiB
C
157 lines
5.0 KiB
C
/*
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* Copyright (c) 2018 Synopsys
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <soc.h>
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#include <init.h>
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#define PMODMUX_BASE_ADDR 0xF0000000
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/*
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* 32-bits, offset 0x0, This register controls mapping of the peripheral device
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* signals on Pmod connectors
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*/
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#define PMOD_MUX_CTRL 0
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/* 32-bits, offset 0x4 */
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#define I2C_MAP_CTRL 1
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/*
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* 32-bits, offset 0x8, SPI_MAP_CTRL[0] selects the mode of operation of the SPI
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* Slave: Normal operation, SPI_MAP_CTRL[0]=0: SPI Slave is connected to Pmod1
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* at connector J1. Loop-back mode, SPI_MAP_CTRL[0]=1: SPI Slave is connected to
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* the SPI Master inside the FPGA using CS4.
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*/
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#define SPI_MAP_CTRL 2
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/*
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* 32-bits, offset 0x8, This register controls the mapping of the UART signals
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* on the Pmod1 connector.
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*/
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#define UART_MAP_CTRL 3
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#define BIT0 (0)
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#define BIT1 (1)
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#define BIT2 (2)
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#define BIT3 (3)
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#define PM1_OFFSET (0)
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#define PM2_OFFSET (4)
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#define PM3_OFFSET (8)
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#define PM4_OFFSET (12)
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#define PM5_OFFSET (16)
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#define PM6_OFFSET (20)
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#define PM7_OFFSET (24)
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#define PM1_MASK (0xf << PM1_OFFSET)
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#define PM2_MASK (0xf << PM2_OFFSET)
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#define PM3_MASK (0xf << PM3_OFFSET)
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#define PM4_MASK (0xf << PM4_OFFSET)
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#define PM5_MASK (0xf << PM5_OFFSET)
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#define PM6_MASK (0xf << PM6_OFFSET)
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#define PM7_MASK (0xf << PM7_OFFSET)
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#define SPI_MAP_NORMAL (0)
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#define SPI_MAP_LOOPBACK (1)
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#define UART_MAP_TYPE4 (0xE4)
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#define UART_MAP_TYPE3 (0x6C)
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/* all pins are configured as GPIO inputs */
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#define PMOD_MUX_CTRL_DEFAULT (0)
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/* normal SPI mode */
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#define SPI_MAP_CTRL_DEFAULT (SPI_MAP_NORMAL)
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/* TYPE4 PMOD compatible */
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#define UART_MAP_CTRL_DEFAULT (UART_MAP_TYPE4)
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/* Pmod1[4:1] are connected to DW GPIO Port C[11:8] */
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#define PM1_UR_GPIO_C ((0 << BIT0) << PM1_OFFSET)
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/* Pmod1[4:1] are connected to DW UART0 signals */
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#define PM1_UR_UART_0 ((1 << BIT0) << PM1_OFFSET)
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/* Pmod1[10:7] are connected to DW GPIO Port A[11:8] */
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#define PM1_LR_GPIO_A ((0 << BIT2) << PM1_OFFSET)
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/* Pmod1[10:7] are connected to DW SPI Slave signals */
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#define PM1_LR_SPI_S ((1 << BIT2) << PM1_OFFSET)
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/*
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* Pmod2[4:1] are connected to DW GPIO Port C[15:12],
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* Pmod2[10:7] are connected to DW GPIO Port A[15:12]
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*/
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#define PM2_GPIO_AC ((0 << BIT0) << PM2_OFFSET)
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/* connect I2C to Pmod2[4:1] and halt/run interface to Pmod2[10:7] */
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#define PM2_I2C_HRI ((1 << BIT0) << PM2_OFFSET)
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/*
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* Pmod3[4:1] are connected to DW GPIO Port C[19:16],
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* Pmod3[10:7] are connected to DW GPIO Port A[19:16]
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*/
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#define PM3_GPIO_AC ((0 << BIT0) << PM3_OFFSET)
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/*
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* Pmod3[4:3] are connected to DW I2C signals,
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* Pmod3[2:1] are connected to DW GPIO Port D[1:0],
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* Pmod3[10:7] are connected to DW GPIO Port D[3:2]
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*/
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#define PM3_I2C_GPIO_D ((1 << BIT0) << PM3_OFFSET)
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/*
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* Pmod4[4:1] are connected to DW GPIO Port C[23:20],
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* Pmod4[10:7] are connected to DW GPIO Port A[23:20]
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*/
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#define PM4_GPIO_AC ((0 << BIT0) << PM4_OFFSET)
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/*
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* Pmod4[4:3] are connected to DW I2C signals,
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* Pmod4[2:1] are connected to DW GPIO Port D[5:4],
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* Pmod4[10:7] are connected to DW GPIO Port D[7:6]
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*/
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#define PM4_I2C_GPIO_D ((1 << BIT0) << PM4_OFFSET)
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/* Pmod5[4:1] are connected to DW GPIO Port C[27:24] */
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#define PM5_UR_GPIO_C ((0 << BIT0) << PM5_OFFSET)
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/* Pmod5[4:1] are connected to DW SPI Master signals using CS1_N */
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#define PM5_UR_SPI_M1 ((1 << BIT0) << PM5_OFFSET)
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/* Pmod5[10:7] are connected to DW GPIO Port A[27:24] */
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#define PM5_LR_GPIO_A ((0 << BIT2) << PM5_OFFSET)
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/* Pmod5[10:7] are connected to DW SPI Master signals using CS2_N */
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#define PM5_LR_SPI_M2 ((1 << BIT2) << PM5_OFFSET)
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/* Pmod6[4:1] are connected to DW GPIO Port C[31:28] */
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#define PM6_UR_GPIO_C ((0 << BIT0) << PM6_OFFSET)
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/* Pmod6[4:1] are connected to DW SPI Master signals using CS0_N */
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#define PM6_UR_SPI_M0 ((1 << BIT0) << PM6_OFFSET)
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/* Pmod6[10:7] are connected to DW GPIO Port A[31:28] */
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#define PM6_LR_GPIO_A ((0 << BIT2) << PM6_OFFSET)
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/*
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* Pmod6[8:7] are connected to the DW SPI Master chip select signals CS1_N and
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* CS2_N, Pmod6[6:5] are connected to the ARC EM halt and sleep status signals
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*/
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#define PM6_LR_CSS_STAT ((1 << BIT2) << PM6_OFFSET)
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static int pmod_mux_init(const struct device *dev)
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{
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volatile uint32_t *mux_regs = (uint32_t *)(PMODMUX_BASE_ADDR);
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mux_regs[SPI_MAP_CTRL] = SPI_MAP_CTRL_DEFAULT;
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mux_regs[UART_MAP_CTRL] = UART_MAP_CTRL_DEFAULT;
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/**
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* + Please refer to corresponding EMSK User Guide for detailed
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* information -> Appendix: A Hardware Functional Description ->
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* Pmods Configuration summary
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* + Set up pin-multiplexer of all PMOD connections
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* - PM1 J1: Upper row as UART 0, lower row as SPI Slave
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* - PM2 J2: IIC 0 and run/halt signals
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* - PM3 J3: GPIO Port A and Port C
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* - PM4 J4: IIC 1 and Port D
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* - PM5 J5: Upper row as SPI Master, lower row as Port A
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* - PM6 J6: Upper row as SPI Master, lower row as Port A
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*/
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mux_regs[PMOD_MUX_CTRL] = PM1_UR_UART_0 | PM1_LR_SPI_S
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| PM2_I2C_HRI | PM3_GPIO_AC
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| PM4_I2C_GPIO_D | PM5_UR_SPI_M1
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| PM5_LR_GPIO_A | PM6_UR_SPI_M0
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| PM6_LR_GPIO_A;
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return 0;
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}
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SYS_INIT(pmod_mux_init, PRE_KERNEL_1,
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CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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