194 lines
3.7 KiB
Plaintext
194 lines
3.7 KiB
Plaintext
/*
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* Copyright 2023 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <arm/armv8-m.dtsi>
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#include <zephyr/dt-bindings/clock/scg_k4.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/pwm/pwm.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-m33f";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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mpu: mpu@e000ed90 {
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compatible = "arm,armv8m-mpu";
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reg = <0xe000ed90 0x40>;
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};
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};
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};
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soc {
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ctcm: sram@14000000 {
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ranges = <0x0 0x14000000 DT_SIZE_K(16)>;
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#address-cells = <1>;
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#size-cells = <1>;
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ctcm0: code_memory@0 {
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compatible = "mmio-sram";
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reg = <0x0 DT_SIZE_K(16)>;
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};
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};
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stcm: sram@30000000 {
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ranges = <0x0 0x30000000 DT_SIZE_K(112)>;
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#address-cells = <1>;
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#size-cells = <1>;
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stcm0: system_memory@0 {
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compatible = "mmio-sram";
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reg = <0x0 DT_SIZE_K(64)>;
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};
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stcm1: system_memory@1a000 {
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compatible = "zephyr,memory-region","mmio-sram";
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reg = <0x1a000 DT_SIZE_K(8)>;
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zephyr,memory-region = "RetainedMem";
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};
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};
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smu2: sram@489c0000 {
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ranges = <0x0 0x489c0000 DT_SIZE_K(40)>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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peripheral: peripheral@50000000 {
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ranges = <0x0 0x50000000 0x10000000>;
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fmu: memory-controller@20000 {
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ranges = <0x0 0x10000000 DT_SIZE_M(1)>;
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "nxp,iap-msf1";
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reg = <0x20000 0x1000>;
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interrupts = <27 0>;
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status = "disabled";
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flash: flash@0 {
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reg = <0x0 DT_SIZE_M(1)>;
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compatible = "soc-nv-flash";
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write-block-size = <16>;
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erase-block-size = <8192>;
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};
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};
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};
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};
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pinctrl: pinctrl {
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compatible = "nxp,kinetis-pinctrl";
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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&peripheral {
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#address-cells = <1>;
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#size-cells = <1>;
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scg: scg@1e000 {
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compatible = "nxp,scg-k4";
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reg = <0x1e000 0x404>;
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#clock-cells = <2>;
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};
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porta: pinmux@42000 {
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compatible = "nxp,kinetis-pinmux";
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reg = <0x42000 0xe0>;
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clocks = <&scg SCG_K4_SLOW_CLK 0x108>;
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};
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portb: pinmux@43000 {
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compatible = "nxp,kinetis-pinmux";
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reg = <0x43000 0xe0>;
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clocks = <&scg SCG_K4_SLOW_CLK 0x10c>;
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};
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portc: pinmux@44000 {
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compatible = "nxp,kinetis-pinmux";
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reg = <0x44000 0xe0>;
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clocks = <&scg SCG_K4_SLOW_CLK 0x110>;
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};
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portd: pinmux@45000 {
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compatible = "nxp,kinetis-pinmux";
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reg = <0x45000 0xe0>;
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clocks = <&scg SCG_K4_SLOW_CLK 0>;
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};
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lpuart0: lpuart@38000 {
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compatible = "nxp,kinetis-lpuart";
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reg = <0x38000 0x34>;
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interrupts = <44 0>;
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clocks = <&scg SCG_K4_FIRC_CLK 0xe0>;
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status = "disabled";
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};
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lpuart1: lpuart@39000 {
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compatible = "nxp,kinetis-lpuart";
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reg = <0x39000 0x34>;
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interrupts = <45 0>;
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clocks = <&scg SCG_K4_FIRC_CLK 0xe4>;
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status = "disabled";
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};
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gpioa: gpio@10000{
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compatible = "nxp,kinetis-gpio";
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status = "disabled";
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gpio-controller;
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#gpio-cells = <2>;
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nxp,kinetis-port = <&porta>;
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reg = <0x10000 0x128>;
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interrupts = <59 0>, <60 0>;
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};
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gpiob: gpio@20000{
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compatible = "nxp,kinetis-gpio";
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status = "disabled";
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gpio-controller;
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#gpio-cells = <2>;
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nxp,kinetis-port = <&portb>;
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reg = <0x20000 0x128>;
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interrupts = <61 0>, <62 0>;
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};
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gpioc: gpio@30000{
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compatible = "nxp,kinetis-gpio";
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status = "disabled";
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gpio-controller;
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#gpio-cells = <2>;
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nxp,kinetis-port = <&portc>;
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reg = <0x30000 0x128>;
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interrupts = <63 0>, <64 0>;
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};
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gpiod: gpio@46000{
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compatible = "nxp,kinetis-gpio";
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status = "disabled";
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gpio-controller;
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#gpio-cells = <2>;
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nxp,kinetis-port = <&portd>;
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reg = <0x46000 0x128>;
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interrupts = <65 0>, <66 0>;
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};
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vbat: vbat@2b000 {
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reg = <0x2b000 0x400>;
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interrupts = <74 0>;
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};
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};
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