583 lines
14 KiB
Plaintext
583 lines
14 KiB
Plaintext
/* SPDX-License-Identifier: Apache-2.0 */
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#include <mem.h>
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#include <arm/armv7-m.dtsi>
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#include <zephyr/dt-bindings/adc/adc.h>
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#include <zephyr/dt-bindings/clock/kinetis_sim.h>
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#include <zephyr/dt-bindings/clock/kinetis_mcg.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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/ {
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aliases {
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watchdog0 = &wdog;
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};
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chosen {
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zephyr,entropy = &rnga;
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zephyr,flash-controller = &ftfe;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m4f";
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reg = <0>;
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};
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};
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/* The on-chip SRAM is split into SRAM_L and SRAM_U regions that form a
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* contiguous block in the memory map, however misaligned accesses
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* across the 0x2000_0000 boundary are not supported in the Arm
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* Cortex-M4 architecture. For clarity and to avoid the temptation for
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* someone to extend sram0 without solving this issue, we define two
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* separate memory nodes here and only use the upper one for now. A
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* potential solution has been proposed in binutils:
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* https://sourceware.org/ml/binutils/2017-02/msg00250.html
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*/
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sram_l: memory@1fff0000 {
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compatible = "zephyr,memory-region", "mmio-sram";
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reg = <0x1fff0000 DT_SIZE_K(64)>;
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zephyr,memory-region = "SRAML";
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};
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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reg = <0x20000000 DT_SIZE_K(192)>;
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};
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temp0: temp0 {
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compatible = "nxp,kinetis-temperature";
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io-channels = <&adc0 26>, <&adc0 27>;
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io-channel-names = "SENSOR", "BANDGAP";
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bandgap-voltage = <1000000>;
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vtemp25 = <716000>;
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sensor-slope-cold = <1620>;
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sensor-slope-hot = <1620>;
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status = "disabled";
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};
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temp1: temp1 {
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compatible = "nxp,kinetis-temperature";
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io-channels = <&adc1 26>, <&adc1 27>;
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io-channel-names = "SENSOR", "BANDGAP";
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bandgap-voltage = <1000000>;
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vtemp25 = <716000>;
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sensor-slope-cold = <1620>;
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sensor-slope-hot = <1620>;
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status = "disabled";
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};
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/* Dummy pinctrl node, filled with pin mux options at board level */
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pinctrl: pinctrl {
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compatible = "nxp,kinetis-pinctrl";
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status = "okay";
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};
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soc {
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mpu: mpu@4000d000 {
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compatible = "nxp,k64f-mpu";
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reg = <0x4000d000 0x824>;
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status = "disabled";
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};
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mcg: clock-controller@40064000 {
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compatible = "nxp,kinetis-mcg";
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reg = <0x40064000 0xd>;
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#clock-cells = <1>;
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};
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osc: clock-controller@40065000 {
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compatible = "nxp,k64f-osc";
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reg = <0x40065000 0x4>;
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enable-external-reference;
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};
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rtc: rtc@4003d000 {
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compatible = "nxp,kinetis-rtc";
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reg = <0x4003d000 0x1000>;
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interrupts = <46 0>, <47 0>;
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interrupt-names = "alarm", "seconds";
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clock-frequency = <32768>;
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prescaler = <32768>;
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};
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sim: sim@40047000 {
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compatible = "nxp,kinetis-sim";
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reg = <0x40047000 0x1060>;
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#clock-cells = <3>;
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core_clk {
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compatible = "fixed-factor-clock";
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clocks = <&mcg KINETIS_MCG_OUT_CLK>;
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clock-div = <1>;
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#clock-cells = <0>;
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};
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bus_clk {
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compatible = "fixed-factor-clock";
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clocks = <&mcg KINETIS_MCG_OUT_CLK>;
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clock-div = <2>;
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#clock-cells = <0>;
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};
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flexbus_clk {
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compatible = "fixed-factor-clock";
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clocks = <&mcg KINETIS_MCG_OUT_CLK>;
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clock-div = <3>;
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#clock-cells = <0>;
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};
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flash_clk {
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compatible = "fixed-factor-clock";
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clocks = <&mcg KINETIS_MCG_OUT_CLK>;
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clock-div = <5>;
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#clock-cells = <0>;
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};
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};
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ftfe: flash-controller@40020000 {
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compatible = "nxp,kinetis-ftfe";
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reg = <0x40020000 0x18>;
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interrupts = <18 0>, <19 0>;
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interrupt-names = "command-complete", "read-collision";
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status = "okay";
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@0 {
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compatible = "soc-nv-flash";
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reg = <0 DT_SIZE_M(1)>;
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erase-block-size = <4096>;
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write-block-size = <8>;
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};
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};
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i2c0: i2c@40066000 {
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compatible = "nxp,kinetis-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40066000 0x1000>;
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interrupts = <24 0>;
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clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 6>;
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status = "disabled";
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};
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i2c1: i2c@40067000 {
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compatible = "nxp,kinetis-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40067000 0x1000>;
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interrupts = <25 0>;
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clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 7>;
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status = "disabled";
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};
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i2c2: i2c@400e6000 {
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compatible = "nxp,kinetis-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x400e6000 0x1000>;
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interrupts = <74 0>;
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clocks = <&sim KINETIS_SIM_BUS_CLK 0x1028 6>;
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status = "disabled";
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};
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uart0: uart@4006a000 {
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compatible = "nxp,kinetis-uart";
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reg = <0x4006a000 0x1000>;
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interrupts = <31 0>, <32 0>;
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interrupt-names = "status", "error";
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clocks = <&sim KINETIS_SIM_CORESYS_CLK 0x1034 10>;
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status = "disabled";
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};
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uart1: uart@4006b000 {
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compatible = "nxp,kinetis-uart";
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reg = <0x4006b000 0x1000>;
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interrupts = <33 0>, <34 0>;
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interrupt-names = "status", "error";
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clocks = <&sim KINETIS_SIM_CORESYS_CLK 0x1034 11>;
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status = "disabled";
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};
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uart2: uart@4006c000 {
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compatible = "nxp,kinetis-uart";
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reg = <0x4006c000 0x1000>;
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interrupts = <35 0>, <36 0>;
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interrupt-names = "status", "error";
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clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 12>;
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status = "disabled";
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};
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uart3: uart@4006d000 {
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compatible = "nxp,kinetis-uart";
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reg = <0x4006d000 0x1000>;
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interrupts = <37 0>, <38 0>;
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interrupt-names = "status", "error";
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clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 13>;
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status = "disabled";
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};
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uart4: uart@400ea000 {
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compatible = "nxp,kinetis-uart";
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reg = <0x400ea000 0x1000>;
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interrupts = <66 0>, <67 0>;
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interrupt-names = "status", "error";
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clocks = <&sim KINETIS_SIM_BUS_CLK 0x1028 10>;
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status = "disabled";
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};
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uart5: uart@400eb000 {
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compatible = "nxp,kinetis-uart";
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reg = <0x400eb000 0x1000>;
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interrupts = <68 0>, <69 0>;
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interrupt-names = "status", "error";
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clocks = <&sim KINETIS_SIM_BUS_CLK 0x1028 11>;
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status = "disabled";
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};
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porta: pinmux@40049000 {
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compatible = "nxp,kinetis-pinmux";
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reg = <0x40049000 0xd0>;
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clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 9>;
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};
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portb: pinmux@4004a000 {
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compatible = "nxp,kinetis-pinmux";
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reg = <0x4004a000 0xd0>;
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clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 10>;
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};
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portc: pinmux@4004b000 {
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compatible = "nxp,kinetis-pinmux";
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reg = <0x4004b000 0xd0>;
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clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 11>;
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};
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portd: pinmux@4004c000 {
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compatible = "nxp,kinetis-pinmux";
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reg = <0x4004c000 0xd0>;
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clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 12>;
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};
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porte: pinmux@4004d000 {
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compatible = "nxp,kinetis-pinmux";
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reg = <0x4004d000 0xd0>;
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clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 13>;
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};
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gpioa: gpio@400ff000 {
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compatible = "nxp,kinetis-gpio";
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status = "disabled";
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reg = <0x400ff000 0x40>;
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interrupts = <59 2>;
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gpio-controller;
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#gpio-cells = <2>;
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nxp,kinetis-port = <&porta>;
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};
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gpiob: gpio@400ff040 {
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compatible = "nxp,kinetis-gpio";
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status = "disabled";
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reg = <0x400ff040 0x40>;
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interrupts = <60 2>;
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gpio-controller;
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#gpio-cells = <2>;
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nxp,kinetis-port = <&portb>;
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};
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gpioc: gpio@400ff080 {
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compatible = "nxp,kinetis-gpio";
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status = "disabled";
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reg = <0x400ff080 0x40>;
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interrupts = <61 2>;
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gpio-controller;
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#gpio-cells = <2>;
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nxp,kinetis-port = <&portc>;
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};
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gpiod: gpio@400ff0c0 {
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compatible = "nxp,kinetis-gpio";
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status = "disabled";
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reg = <0x400ff0c0 0x40>;
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interrupts = <62 2>;
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gpio-controller;
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#gpio-cells = <2>;
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nxp,kinetis-port = <&portd>;
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};
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gpioe: gpio@400ff100 {
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compatible = "nxp,kinetis-gpio";
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status = "disabled";
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reg = <0x400ff100 0x40>;
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interrupts = <63 2>;
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gpio-controller;
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#gpio-cells = <2>;
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nxp,kinetis-port = <&porte>;
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};
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spi0: spi@4002c000 {
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compatible = "nxp,kinetis-dspi";
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reg = <0x4002c000 0x88>;
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interrupts = <26 3>;
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dmas = <&edma0 0 14>, <&edma0 0 15>;
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dma-names = "rx", "tx";
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rx-fifo-size = <4>;
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tx-fifo-size = <4>;
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clocks = <&sim KINETIS_SIM_BUS_CLK 0x103C 12>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi1: spi@4002d000 {
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compatible = "nxp,kinetis-dspi";
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reg = <0x4002d000 0x88>;
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interrupts = <27 3>;
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dmas = <&edma0 0 16>, <&edma0 0 16>;
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dma-names = "rx", "tx";
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rx-fifo-size = <1>;
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tx-fifo-size = <1>;
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nxp,rx-tx-chn-share;
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clocks = <&sim KINETIS_SIM_BUS_CLK 0x103C 13>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi2: spi@400ac000 {
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compatible = "nxp,kinetis-dspi";
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reg = <0x400ac000 0x88>;
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interrupts = <65 3>;
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dmas = <&edma0 0 38>, <&edma0 0 39>;
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dma-names = "rx", "tx";
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rx-fifo-size = <1>;
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tx-fifo-size = <1>;
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nxp,rx-tx-chn-share;
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clocks = <&sim KINETIS_SIM_BUS_CLK 0x1030 12>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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wdog: watchdog@40052000 {
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compatible = "nxp,kinetis-wdog";
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reg = <0x40052000 16>;
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interrupts = <22 0>;
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clocks = <&sim KINETIS_SIM_LPO_CLK 0 0>;
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};
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ftm0: ftm@40038000{
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compatible = "nxp,kinetis-ftm";
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reg = <0x40038000 0x98>;
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interrupts = <42 0>;
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clocks = <&mcg KINETIS_MCG_FIXED_FREQ_CLK>;
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prescaler = <16>;
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status = "disabled";
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};
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ftm1: ftm@40039000{
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compatible = "nxp,kinetis-ftm";
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reg = <0x40039000 0x98>;
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interrupts = <43 0>;
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clocks = <&mcg KINETIS_MCG_FIXED_FREQ_CLK>;
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prescaler = <16>;
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status = "disabled";
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};
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ftm2: ftm@4003a000{
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compatible = "nxp,kinetis-ftm";
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reg = <0x4003a000 0x98>;
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interrupts = <44 0>;
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clocks = <&mcg KINETIS_MCG_FIXED_FREQ_CLK>;
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prescaler = <16>;
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status = "disabled";
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};
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ftm3: ftm@400b9000{
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compatible = "nxp,kinetis-ftm";
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reg = <0x400b9000 0x98>;
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interrupts = <71 0>;
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clocks = <&mcg KINETIS_MCG_FIXED_FREQ_CLK>;
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prescaler = <16>;
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status = "disabled";
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};
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adc0: adc@4003b000{
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compatible = "nxp,kinetis-adc16";
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reg = <0x4003b000 0x70>;
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clocks = <&sim KINETIS_SIM_SIM_SOPT7 0 0xF>,
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<&sim KINETIS_SIM_SIM_SOPT7 7 0x80>;
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dmas = <&edma0 0 40>;
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dma-names = "adc0";
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clk-source = <0>;
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interrupts = <39 0>;
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status = "disabled";
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#io-channel-cells = <1>;
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};
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adc1: adc@400bb000{
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compatible = "nxp,kinetis-adc16";
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reg = <0x400bb000 0x70>;
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clocks = <&sim KINETIS_SIM_SIM_SOPT7 8 0xF00>,
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<&sim KINETIS_SIM_SIM_SOPT7 15 0x8000>;
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dmas = <&edma0 0 41>;
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dma-names = "adc1";
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clk-source = <0>;
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interrupts = <73 0>;
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status = "disabled";
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#io-channel-cells = <1>;
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};
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dac0: dac@400cc000 {
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compatible = "nxp,kinetis-dac";
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reg = <0x400cc000 0x1000>;
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interrupts = <56 0>;
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voltage-reference = <1>;
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status = "disabled";
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#io-channel-cells = <1>;
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};
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dac1: dac@400cd000 {
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compatible = "nxp,kinetis-dac";
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reg = <0x400cd000 0x1000>;
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interrupts = <72 0>;
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voltage-reference = <1>;
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status = "disabled";
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#io-channel-cells = <1>;
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};
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usbotg: usbd@40072000 {
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compatible = "nxp,kinetis-usbd";
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reg = <0x40072000 0x1000>;
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interrupts = <53 1>;
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interrupt-names = "usb_otg";
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num-bidir-endpoints = <16>;
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status = "disabled";
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};
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enet: ethernet@400c0000 {
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compatible = "nxp,enet";
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reg = <0x400c0000 0x620>;
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clocks = <&sim KINETIS_SIM_ENET_CLK 0 0>;
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enet_mac: ethernet {
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compatible = "nxp,enet-mac";
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interrupts = <83 0>, <84 0>, <85 0>;
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interrupt-names = "TX", "RX", "ERR";
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nxp,mdio = <&enet_mdio>;
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nxp,ptp-clock = <&enet_ptp_clock>;
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phy-connection-type = "rmii";
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status = "disabled";
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};
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enet_mdio: mdio {
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compatible = "nxp,enet-mdio";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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enet_ptp_clock: ptp_clock {
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compatible = "nxp,enet-ptp-clock";
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interrupts = <82 0>;
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interrupt-names = "IEEE1588_TMR";
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clocks = <&sim KINETIS_SIM_ENET_1588_CLK 0 0>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
rnga: random@40029000 {
|
|
compatible = "nxp,kinetis-rnga";
|
|
reg = <0x40029000 0x1000>;
|
|
status = "okay";
|
|
interrupts = <23 0>;
|
|
};
|
|
|
|
flexcan0: can@40024000 {
|
|
compatible = "nxp,flexcan";
|
|
reg = <0x40024000 0x1000>;
|
|
interrupts = <75 0>, <76 0>, <77 0>, <78 0>, <79 0>, <80 0>;
|
|
interrupt-names = "mb-0-15", "bus-off", "error", "tx-warning", "rx-warning", "wake-up";
|
|
clocks = <&sim KINETIS_SIM_BUS_CLK 0x103C 4>;
|
|
clk-source = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
edma0: dma-controller@40008000 {
|
|
#dma-cells = <2>;
|
|
compatible = "nxp,mcux-edma";
|
|
dma-channels = <16>;
|
|
dma-requests = <64>;
|
|
nxp,mem2mem;
|
|
reg = <0x40008000 0x1000>,
|
|
<0x40021000 0x1000>;
|
|
interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
|
|
<4 0>, <5 0>, <6 0>, <7 0>,
|
|
<8 0>, <9 0>, <10 0>, <11 0>,
|
|
<12 0>, <13 0>, <14 0>, <15 0>,
|
|
<16 0>;
|
|
clocks = <&sim KINETIS_SIM_DMA_CLK 0x1040 0x00000002>,
|
|
<&sim KINETIS_SIM_DMAMUX_CLK 0x103C 0x00000002>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pit0: pit@40037000 {
|
|
compatible = "nxp,pit";
|
|
reg = <0x40037000 0x1000>;
|
|
clocks = <&sim KINETIS_SIM_BUS_CLK 0x103c 23>;
|
|
status = "disabled";
|
|
max-load-value = <0xffffffff>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
pit0_channel0: pit0_channel@0 {
|
|
compatible = "nxp,pit-channel";
|
|
reg = <0>;
|
|
interrupts = <48 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pit0_channel1: pit0_channel@1 {
|
|
compatible = "nxp,pit-channel";
|
|
reg = <1>;
|
|
interrupts = <49 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pit0_channel2: pit0_channel@2 {
|
|
compatible = "nxp,pit-channel";
|
|
reg = <2>;
|
|
interrupts = <50 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pit0_channel3: pit0_channel@3 {
|
|
compatible = "nxp,pit-channel";
|
|
reg = <3>;
|
|
interrupts = <51 0>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&nvic {
|
|
arm,num-irq-priority-bits = <4>;
|
|
};
|