80 lines
2.5 KiB
C
80 lines
2.5 KiB
C
/*
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* Copyright (c) 2021 Intel Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <gen_offset.h>
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#include <kernel_offsets.h>
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#include <zephyr/arch/xtensa/thread.h>
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#include <xtensa_asm2_context.h>
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GEN_ABSOLUTE_SYM(___xtensa_irq_bsa_t_SIZEOF, sizeof(_xtensa_irq_bsa_t));
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GEN_ABSOLUTE_SYM(___xtensa_irq_stack_frame_raw_t_SIZEOF, sizeof(_xtensa_irq_stack_frame_raw_t));
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GEN_ABSOLUTE_SYM(___xtensa_irq_stack_frame_a15_t_SIZEOF, sizeof(_xtensa_irq_stack_frame_a15_t));
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GEN_ABSOLUTE_SYM(___xtensa_irq_stack_frame_a11_t_SIZEOF, sizeof(_xtensa_irq_stack_frame_a11_t));
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GEN_ABSOLUTE_SYM(___xtensa_irq_stack_frame_a7_t_SIZEOF, sizeof(_xtensa_irq_stack_frame_a7_t));
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GEN_ABSOLUTE_SYM(___xtensa_irq_stack_frame_a3_t_SIZEOF, sizeof(_xtensa_irq_stack_frame_a3_t));
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GEN_OFFSET_SYM(_xtensa_irq_bsa_t, a0);
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GEN_OFFSET_SYM(_xtensa_irq_bsa_t, scratch);
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GEN_OFFSET_SYM(_xtensa_irq_bsa_t, a2);
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GEN_OFFSET_SYM(_xtensa_irq_bsa_t, a3);
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GEN_OFFSET_SYM(_xtensa_irq_bsa_t, exccause);
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GEN_OFFSET_SYM(_xtensa_irq_bsa_t, pc);
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GEN_OFFSET_SYM(_xtensa_irq_bsa_t, ps);
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GEN_OFFSET_SYM(_xtensa_irq_bsa_t, sar);
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#if XCHAL_HAVE_LOOPS
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GEN_OFFSET_SYM(_xtensa_irq_bsa_t, lcount);
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GEN_OFFSET_SYM(_xtensa_irq_bsa_t, lbeg);
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GEN_OFFSET_SYM(_xtensa_irq_bsa_t, lend);
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#endif
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#if XCHAL_HAVE_S32C1I
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GEN_OFFSET_SYM(_xtensa_irq_bsa_t, scompare1);
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#endif
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#if XCHAL_HAVE_THREADPTR
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GEN_OFFSET_SYM(_xtensa_irq_bsa_t, threadptr);
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#endif
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#if XCHAL_HAVE_FP && defined(CONFIG_CPU_HAS_FPU) && defined(CONFIG_FPU_SHARING)
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GEN_OFFSET_SYM(_xtensa_irq_bsa_t, fcr);
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GEN_OFFSET_SYM(_xtensa_irq_bsa_t, fsr);
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GEN_OFFSET_SYM(_xtensa_irq_bsa_t, fpu0);
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GEN_OFFSET_SYM(_xtensa_irq_bsa_t, fpu1);
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GEN_OFFSET_SYM(_xtensa_irq_bsa_t, fpu2);
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GEN_OFFSET_SYM(_xtensa_irq_bsa_t, fpu3);
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GEN_OFFSET_SYM(_xtensa_irq_bsa_t, fpu4);
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GEN_OFFSET_SYM(_xtensa_irq_bsa_t, fpu5);
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GEN_OFFSET_SYM(_xtensa_irq_bsa_t, fpu6);
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GEN_OFFSET_SYM(_xtensa_irq_bsa_t, fpu7);
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GEN_OFFSET_SYM(_xtensa_irq_bsa_t, fpu8);
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GEN_OFFSET_SYM(_xtensa_irq_bsa_t, fpu9);
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GEN_OFFSET_SYM(_xtensa_irq_bsa_t, fpu10);
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GEN_OFFSET_SYM(_xtensa_irq_bsa_t, fpu11);
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GEN_OFFSET_SYM(_xtensa_irq_bsa_t, fpu12);
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GEN_OFFSET_SYM(_xtensa_irq_bsa_t, fpu13);
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GEN_OFFSET_SYM(_xtensa_irq_bsa_t, fpu14);
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GEN_OFFSET_SYM(_xtensa_irq_bsa_t, fpu15);
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#endif
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#if defined(CONFIG_XTENSA_HIFI_SHARING)
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GEN_OFFSET_SYM(_xtensa_irq_bsa_t, hifi);
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#endif
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#ifdef CONFIG_USERSPACE
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GEN_OFFSET_SYM(_thread_arch_t, psp);
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#ifdef CONFIG_XTENSA_MMU
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GEN_OFFSET_SYM(_thread_arch_t, ptables);
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#endif
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#ifdef CONFIG_XTENSA_MPU
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GEN_OFFSET_SYM(_thread_arch_t, mpu_map);
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#endif
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#endif
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GEN_ABS_SYM_END
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