200 lines
5.3 KiB
Plaintext
200 lines
5.3 KiB
Plaintext
# IA32-specific X86 subarchitecture options
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# Copyright (c) 2019 Intel Corp.
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# SPDX-License-Identifier: Apache-2.0
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if !X86_64
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config NESTED_INTERRUPTS
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bool "Nested interrupts"
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default y
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help
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This option enables support for nested interrupts.
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menu "Memory Layout Options"
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config IDT_NUM_VECTORS
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int "Number of IDT vectors"
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default 256
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range 32 256
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help
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This option specifies the number of interrupt vector entries in the
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Interrupt Descriptor Table (IDT). By default all 256 vectors are
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supported in an IDT requiring 2048 bytes of memory.
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config SET_GDT
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bool "Setup GDT as part of boot process"
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default y
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help
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This option sets up the GDT as part of the boot process. However,
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this may conflict with some security scenarios where the GDT is
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already appropriately set by an earlier bootloader stage, in which
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case this should be disabled. If disabled, the global _gdt pointer
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will not be available.
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config GDT_DYNAMIC
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bool "Store GDT in RAM so that it can be modified"
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depends on SET_GDT
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help
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This option stores the GDT in RAM instead of ROM, so that it may
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be modified at runtime at the expense of some memory.
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config GDT_RESERVED_NUM_ENTRIES
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int "Number of reserved GDT entry place holders"
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depends on GDT_DYNAMIC
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default 0
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help
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This option defines the number of GDT entry place holders revserved
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that can be filled at runtime.
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endmenu
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menu "Processor Capabilities"
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config X86_ENABLE_TSS
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bool
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help
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This hidden option enables defining a Task State Segment (TSS) for
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kernel execution. This is needed to handle double-faults or
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do privilege elevation. It also defines a special TSS and handler
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for correctly handling double-fault exceptions, instead of just
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letting the system triple-fault and reset.
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config X86_STACK_PROTECTION
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bool
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default y if HW_STACK_PROTECTION
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select THREAD_STACK_INFO
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select SET_GDT
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select GDT_DYNAMIC
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select X86_ENABLE_TSS
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imply THREAD_STACK_MEM_MAPPED if !DEMAND_PAGING
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help
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This option leverages the MMU to cause a system fatal error if the
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bounds of the current process stack are overflowed. This is done
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by preceding all stack areas with a 4K guard page.
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config X86_USERSPACE
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bool
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default y if USERSPACE
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select THREAD_STACK_INFO
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select SET_GDT
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select GDT_DYNAMIC
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select X86_ENABLE_TSS
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help
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This option enables APIs to drop a thread's privileges down to ring 3,
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supporting user-level threads that are protected from each other and
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from crashing the kernel.
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config X86_PAE
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bool "Use PAE page tables"
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default y
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depends on X86_MMU
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help
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If enabled, use PAE-style page tables instead of 32-bit page tables.
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The advantage is support for the Execute Disable bit, at a cost of
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more memory for paging structures.
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menu "Architecture Floating Point Options"
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if CPU_HAS_FPU
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config SSE
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bool "SSE registers"
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depends on FPU
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select X86_SSE
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help
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This option is deprecated. Please use CONFIG_X86_SSE instead.
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config SSE_FP_MATH
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bool "Compiler-generated SSEx instructions"
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depends on X86_SSE
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select X86_SSE_FP_MATH
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help
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This option is deprecated. Please use CONFIG_X86_SSE_FP_MATH instead.
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config EAGER_FPU_SHARING
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bool
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depends on FPU
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depends on USERSPACE
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default y if !X86_NO_LAZY_FP
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help
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This hidden option unconditionally saves/restores the FPU/SIMD
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register state on every context switch.
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Mitigates CVE-2018-3665, but incurs a performance hit.
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For vulnerable systems that process sensitive information in the
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FPU register set, should be used any time CONFIG_FPU is
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enabled, regardless if the FPU is used by one thread or multiple.
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config LAZY_FPU_SHARING
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bool
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depends on FPU
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depends on !EAGER_FPU_SHARING
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depends on FPU_SHARING
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default y if X86_NO_LAZY_FP || !USERSPACE
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help
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This hidden option allows multiple threads to use the floating point
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registers, using logic to lazily save/restore the floating point
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register state on context switch.
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On Intel Core processors, may be vulnerable to exploits which allows
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malware to read the contents of all floating point registers, see
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CVE-2018-3665.
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endif # CPU_HAS_FPU
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config X86_FP_USE_SOFT_FLOAT
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bool
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default y if !FPU
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help
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Enable using software floating point operations.
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endmenu
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config X86_DYNAMIC_IRQ_STUBS
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int "Number of dynamic interrupt stubs"
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depends on DYNAMIC_INTERRUPTS
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default 4
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help
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Installing interrupt handlers with irq_connect_dynamic() requires
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some stub code to be generated at build time, one stub per dynamic
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interrupt.
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endmenu
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config ARCH_HAS_STACKWALK
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bool
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default y
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select DEBUG_INFO
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select THREAD_STACK_INFO
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depends on !OMIT_FRAME_POINTER
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help
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Internal config to indicate that the arch_stack_walk() API is implemented
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and it can be enabled.
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config X86_USE_THREAD_LOCAL_STORAGE
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bool
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default y if THREAD_LOCAL_STORAGE
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select SET_GDT
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select GDT_DYNAMIC
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help
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Internal config to enable thread local storage.
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config X86_MFENCE_INSTRUCTION_SUPPORTED
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bool "X86 MFENCE instruction supported"
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default y
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depends on CACHE_MANAGEMENT
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help
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Set n to disable the use of MFENCE instruction in arch_dcache_flush()
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for X86 CPUs have CLFLUSH instruction but no MFENCE
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config X86_RUNTIME_IRQ_STATS
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bool
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help
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Add irq runtime statistics to allow runtime profiling irq performance
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data with Host tools, enable this and implement platform dependent API
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runtime_irq_stats().
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endif # !X86_64
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