244 lines
6.2 KiB
C
244 lines
6.2 KiB
C
/*
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* Copyright (c) 2018 Intel Corporation
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* Copyright (c) 2019 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT worldsemi_ws2812_gpio
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#include <drivers/led_strip.h>
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#include <string.h>
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#define LOG_LEVEL CONFIG_LED_STRIP_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(ws2812_gpio);
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#include <zephyr.h>
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#include <soc.h>
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#include <drivers/gpio.h>
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#include <device.h>
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#include <drivers/clock_control.h>
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#include <drivers/clock_control/nrf_clock_control.h>
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struct ws2812_gpio_data {
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struct device *gpio;
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struct device *clk;
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};
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struct ws2812_gpio_cfg {
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u8_t pin;
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bool has_white;
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};
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static struct ws2812_gpio_data *dev_data(struct device *dev)
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{
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return dev->driver_data;
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}
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static const struct ws2812_gpio_cfg *dev_cfg(struct device *dev)
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{
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return dev->config->config_info;
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}
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/*
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* This is hard-coded to nRF51 in two ways:
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*
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* 1. The assembly delays T1H, T0H, TxL
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* 2. GPIO set/clear
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*/
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/*
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* T1H: 1 bit high pulse delay: 12 cycles == .75 usec
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* T0H: 0 bit high pulse delay: 4 cycles == .25 usec
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* TxL: inter-bit low pulse delay: 8 cycles == .5 usec
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*
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* We can't use k_busy_wait() here: its argument is in microseconds,
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* and we need roughly .05 microsecond resolution.
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*/
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#define DELAY_T1H "nop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\n"
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#define DELAY_T0H "nop\nnop\nnop\nnop\n"
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#define DELAY_TxL "nop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\n"
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/*
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* GPIO set/clear (these make assumptions about assembly details
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* below).
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*
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* This uses OUTCLR == OUTSET+4.
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*
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* We should be able to make this portable using the results of
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* https://github.com/zephyrproject-rtos/zephyr/issues/11917.
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*
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* We already have the GPIO device stashed in ws2812_gpio_data, so
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* this driver can be used as a test case for the optimized API.
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*
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* Per Arm docs, both Rd and Rn must be r0-r7, so we use the "l"
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* constraint in the below assembly.
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*/
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#define SET_HIGH "str %[p], [%[r], #0]\n" /* OUTSET = BIT(LED_PIN) */
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#define SET_LOW "str %[p], [%[r], #4]\n" /* OUTCLR = BIT(LED_PIN) */
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/* Send out a 1 bit's pulse */
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#define ONE_BIT(base, pin) do { \
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__asm volatile (SET_HIGH \
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DELAY_T1H \
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SET_LOW \
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DELAY_TxL \
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:: \
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[r] "l" (base), \
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[p] "l" (pin)); } while (0)
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/* Send out a 0 bit's pulse */
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#define ZERO_BIT(base, pin) do { \
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__asm volatile (SET_HIGH \
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DELAY_T0H \
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SET_LOW \
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DELAY_TxL \
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:: \
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[r] "l" (base), \
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[p] "l" (pin)); } while (0)
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static int send_buf(struct device *dev, u8_t *buf, size_t len)
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{
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volatile u32_t *base = (u32_t *)&NRF_GPIO->OUTSET;
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const u32_t val = BIT(dev_cfg(dev)->pin);
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struct device *clk = dev_data(dev)->clk;
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unsigned int key;
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int rc;
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rc = clock_control_on(clk, CLOCK_CONTROL_NRF_SUBSYS_HF);
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if (rc) {
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return rc;
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}
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key = irq_lock();
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while (len--) {
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u32_t b = *buf++;
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s32_t i;
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/*
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* Generate signal out of the bits, MSbit first.
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*
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* Accumulator maintenance and branching mean the
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* inter-bit time will be longer than TxL, but the
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* wp.josh.com blog post says we have at least 5 usec
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* of slack time between bits before we risk the
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* signal getting latched, so this will be fine as
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* long as the compiler does something minimally
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* reasonable.
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*/
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for (i = 7; i >= 0; i--) {
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if (b & BIT(i)) {
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ONE_BIT(base, val);
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} else {
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ZERO_BIT(base, val);
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}
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}
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}
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irq_unlock(key);
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rc = clock_control_off(clk, CLOCK_CONTROL_NRF_SUBSYS_HF);
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return rc;
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}
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static int ws2812_gpio_update_rgb(struct device *dev, struct led_rgb *pixels,
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size_t num_pixels)
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{
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const struct ws2812_gpio_cfg *config = dev->config->config_info;
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const bool has_white = config->has_white;
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u8_t *ptr = (u8_t *)pixels;
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size_t i;
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/* Convert from RGB to on-wire format (GRB or GRBW) */
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for (i = 0; i < num_pixels; i++) {
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u8_t r = pixels[i].r;
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u8_t g = pixels[i].g;
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u8_t b = pixels[i].b;
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*ptr++ = g;
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*ptr++ = r;
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*ptr++ = b;
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if (has_white) {
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*ptr++ = 0; /* white channel is unused */
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}
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}
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return send_buf(dev, (u8_t *)pixels, num_pixels * (has_white ? 4 : 3));
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}
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static int ws2812_gpio_update_channels(struct device *dev, u8_t *channels,
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size_t num_channels)
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{
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LOG_ERR("update_channels not implemented");
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return -ENOTSUP;
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}
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static const struct led_strip_driver_api ws2812_gpio_api = {
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.update_rgb = ws2812_gpio_update_rgb,
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.update_channels = ws2812_gpio_update_channels,
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};
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#define WS2812_GPIO_LABEL(idx) \
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(DT_INST_LABEL(idx))
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#define WS2812_GPIO_HAS_WHITE(idx) \
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(DT_INST_PROP(idx, has_white_channel) == 1)
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#define WS2812_GPIO_DEV(idx) \
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(DT_INST_GPIO_LABEL(idx, in_gpios))
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#define WS2812_GPIO_PIN(idx) \
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(DT_INST_GPIO_PIN(idx, in_gpios))
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#define WS2812_GPIO_FLAGS(idx) \
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(DT_INST_GPIO_FLAGS(idx, in_gpios))
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/*
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* The inline assembly above is designed to work on nRF51 devices with
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* the 16 MHz clock enabled.
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*
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* TODO: try to make this portable, or at least port to more devices.
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*/
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#define WS2812_GPIO_CLK(idx) DT_LABEL(DT_INST(0, nordic_nrf_clock))
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#define WS2812_GPIO_DEVICE(idx) \
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\
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static int ws2812_gpio_##idx##_init(struct device *dev) \
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{ \
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struct ws2812_gpio_data *data = dev_data(dev); \
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\
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data->gpio = device_get_binding(WS2812_GPIO_DEV(idx)); \
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if (!data->gpio) { \
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LOG_ERR("Unable to find GPIO controller %s", \
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WS2812_GPIO_DEV(idx)); \
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return -ENODEV; \
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} \
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\
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data->clk = device_get_binding(WS2812_GPIO_CLK(idx)); \
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if (!data->clk) { \
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LOG_ERR("Unable to find clock %s", \
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WS2812_GPIO_CLK(idx)); \
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return -ENODEV; \
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} \
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\
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return gpio_pin_configure(data->gpio, \
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WS2812_GPIO_PIN(idx), \
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WS2812_GPIO_FLAGS(idx) | \
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GPIO_OUTPUT); \
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} \
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\
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static struct ws2812_gpio_data ws2812_gpio_##idx##_data; \
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\
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static const struct ws2812_gpio_cfg ws2812_gpio_##idx##_cfg = { \
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.pin = WS2812_GPIO_PIN(idx), \
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.has_white = WS2812_GPIO_HAS_WHITE(idx), \
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}; \
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\
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DEVICE_AND_API_INIT(ws2812_gpio_##idx, WS2812_GPIO_LABEL(idx), \
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ws2812_gpio_##idx##_init, \
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&ws2812_gpio_##idx##_data, \
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&ws2812_gpio_##idx##_cfg, POST_KERNEL, \
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CONFIG_LED_STRIP_INIT_PRIORITY, \
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&ws2812_gpio_api)
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DT_INST_FOREACH(WS2812_GPIO_DEVICE)
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