zephyr/soc/intel
Kai Vehmanen 010f39a409 soc: intel_adsp_cavs: store PS when power gating secondary core
When non-primary core is powered down and restart with sequence of:
 - PM state set to SOFT_OFF
 - once target core is idle, cut power with soc_adsp_halt_cpu()
 - power up core again with k_smp_cpu_resume()

The execution will continue from stored DSP core context, but
will hit an assert in z_smp_cpu_mobile() as the PS.INTLEVEL
is zero.

Fix this issue by storing and restoring PS register in this flow.

Link: https://github.com/zephyrproject-rtos/zephyr/issues/70181
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2024-03-15 18:16:51 -04:00
..
alder_lake
apollo_lake
atom
elkhart_lake
intel_adsp soc: intel_adsp_cavs: store PS when power gating secondary core 2024-03-15 18:16:51 -04:00
intel_ish
intel_niosv
intel_socfpga
intel_socfpga_std
lakemont
raptor_lake