be881d4cf2
On Intel ADSP platforms, additional "isync" is needed in interrupt vector to synchronize icache when core is woken up from deeper sleep state by an interrupt. This is only needed if DSP clock gating is enabled. Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com> |
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arc | ||
arm | ||
arm64 | ||
common | ||
mips | ||
nios2 | ||
posix | ||
riscv | ||
sparc | ||
x86 | ||
xtensa | ||
CMakeLists.txt | ||
Kconfig | ||
Kconfig.v1 | ||
Kconfig.v2 | ||
archs.yml |