zephyr/arch
Kai Vehmanen be881d4cf2 arch: xtensa: add isync to interrupt vector
On Intel ADSP platforms, additional "isync" is needed in interrupt
vector to synchronize icache when core is woken up from deeper
sleep state by an interrupt. This is only needed if DSP clock
gating is enabled.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2024-03-15 21:45:57 -04:00
..
arc hwmv2: Introduce Hardware model version 2 and convert devices 2024-03-02 16:56:33 -05:00
arm llext: arm: Add R_ARM_ARM_THM_CALL reloc support 2024-03-14 19:07:49 +00:00
arm64 arch: arm64: correct a comment on CONFIG_ARM64_STACK_PROTECTION 2024-03-11 08:16:06 -04:00
common hwmv2: Introduce Hardware model version 2 and convert devices 2024-03-02 16:56:33 -05:00
mips
nios2
posix arch/posix cmake: Replace native_posix w native_sim and use hwmv2 names 2024-03-15 16:13:12 +01:00
riscv arch: riscv: introduce a Kconfig to mask `mhartid` 2024-03-13 11:10:25 +00:00
sparc
x86 x86: use CONFIG_PRIVILEGED_STACK_SIZE for stack size 2024-03-08 09:37:36 +01:00
xtensa arch: xtensa: add isync to interrupt vector 2024-03-15 21:45:57 -04:00
CMakeLists.txt
Kconfig hwmv2: Introduce Hardware model version 2 and convert devices 2024-03-02 16:56:33 -05:00
Kconfig.v1 hwmv2: Introduce Hardware model version 2 and convert devices 2024-03-02 16:56:33 -05:00
Kconfig.v2 hwmv2: Introduce Hardware model version 2 and convert devices 2024-03-02 16:56:33 -05:00
archs.yml hwmv2: Introduce Hardware model version 2 and convert devices 2024-03-02 16:56:33 -05:00