98 lines
2.0 KiB
C
98 lines
2.0 KiB
C
/*
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* Copyright (c) 2019 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief System/hardware module for STM32H7 CM7 processor
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*/
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#include <kernel.h>
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#include <device.h>
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#include <init.h>
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#include <soc.h>
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#include <arch/cpu.h>
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#include <arch/arm/cortex_m/cmsis.h>
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#if defined(CONFIG_STM32H7_DUAL_CORE)
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static int stm32h7_m4_wakeup(struct device *arg)
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{
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/*HW semaphore Clock enable*/
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LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_HSEM);
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if (IS_ENABLED(CONFIG_STM32H7_BOOT_CM4_CM7)) {
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int timeout;
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/*
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* When system initialization is finished, Cortex-M7 will
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* release Cortex-M4 by means of HSEM notification
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*/
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/*Take HSEM */
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LL_HSEM_1StepLock(HSEM, LL_HSEM_ID_0);
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/*Release HSEM in order to notify the CPU2(CM4)*/
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LL_HSEM_ReleaseLock(HSEM, LL_HSEM_ID_0, 0);
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/* wait until CPU2 wakes up from stop mode */
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timeout = 0xFFFF;
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while ((LL_RCC_D2CK_IsReady() == 0) && ((timeout--) > 0)) {
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}
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if (timeout < 0) {
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return -EIO;
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}
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} else if (IS_ENABLED(CONFIG_STM32H7_BOOT_CM7_CM4GATED)) {
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/* Start CM4 */
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LL_RCC_ForceCM4Boot();
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}
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return 0;
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}
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#endif /* CONFIG_STM32H7_DUAL_CORE */
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/**
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* @brief Perform basic hardware initialization at boot.
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*
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* This needs to be run from the very beginning.
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* So the init priority has to be 0 (zero).
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*
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* @return 0
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*/
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static int stm32h7_init(struct device *arg)
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{
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u32_t key;
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ARG_UNUSED(arg);
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key = irq_lock();
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SCB_EnableICache();
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if (!(SCB->CCR & SCB_CCR_DC_Msk)) {
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SCB_EnableDCache();
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}
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/* Install default handler that simply resets the CPU
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* if configured in the kernel, NOP otherwise
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*/
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NMI_INIT();
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irq_unlock(key);
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/* Update CMSIS SystemCoreClock variable (HCLK) */
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/* At reset, system core clock is set to 64 MHz from HSI */
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SystemCoreClock = 64000000;
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return 0;
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}
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SYS_INIT(stm32h7_init, PRE_KERNEL_1, 0);
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#if defined(CONFIG_STM32H7_DUAL_CORE)
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/* Unlock M4 once system configuration has been done */
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SYS_INIT(stm32h7_m4_wakeup, POST_KERNEL, CONFIG_APPLICATION_INIT_PRIORITY);
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#endif /* CONFIG_STM32H7_DUAL_CORE */
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