80 lines
1.8 KiB
C
80 lines
1.8 KiB
C
/*
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* Copyright (c) 2017 RnDity Sp. z o.o.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief System/hardware module for STM32F0 processor
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*/
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#include <device.h>
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#include <init.h>
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#include <arch/cpu.h>
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#include <arch/arm/cortex_m/cmsis.h>
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#include <linker/linker-defs.h>
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#include <string.h>
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/**
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* @brief Relocate vector table to SRAM.
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*
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* On Cortex-M0 platforms, the Vector Base address cannot be changed.
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*
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* A Zephyr image that is run from the mcuboot bootloader must relocate the
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* vector table to SRAM to be able to replace the vectors pointing to the
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* bootloader.
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*
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* A zephyr image that is a bootloader does not have to relocate the
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* vector table.
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*
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* Replaces the default function from prep_c.c.
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*
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* @note Zephyr applications that will not be loaded by a bootloader should
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* pretend to be a bootloader if the SRAM vector table is not needed.
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*/
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void relocate_vector_table(void)
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{
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#ifndef CONFIG_IS_BOOTLOADER
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extern char _ram_vector_start[];
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size_t vector_size = (size_t)_vector_end - (size_t)_vector_start;
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memcpy(_ram_vector_start, _vector_start, vector_size);
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LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_SRAM);
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#endif
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}
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/**
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* @brief Perform basic hardware initialization at boot.
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*
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* This needs to be run from the very beginning.
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* So the init priority has to be 0 (zero).
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*
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* @return 0
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*/
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static int stm32f0_init(struct device *arg)
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{
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u32_t key;
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ARG_UNUSED(arg);
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key = irq_lock();
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/* Install default handler that simply resets the CPU
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* if configured in the kernel, NOP otherwise
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*/
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NMI_INIT();
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irq_unlock(key);
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/* Update CMSIS SystemCoreClock variable (HCLK) */
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/* At reset, system core clock is set to 8 MHz from HSI */
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SystemCoreClock = 8000000;
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return 0;
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}
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SYS_INIT(stm32f0_init, PRE_KERNEL_1, 0);
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