94 lines
1.8 KiB
Plaintext
94 lines
1.8 KiB
Plaintext
/*
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* Copyright (c) 2017 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "skeleton.dtsi"
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#include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "intel,x86";
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d-cache-line-size = <64>;
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reg = <0>;
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};
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};
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intc: ioapic@fec00000 {
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compatible = "intel,ioapic";
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#address-cells = <1>;
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#interrupt-cells = <3>;
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reg = <0xfec00000 0x1000>;
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interrupt-controller;
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};
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intc_loapic: loapic@fee00000 {
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compatible = "intel,loapic";
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reg = <0xfee00000 0x1000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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#address-cells = <1>;
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};
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dram0: memory@0 {
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device_type = "memory";
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reg = <DT_DRAM_BASE DT_DRAM_SIZE>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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uart0: uart@3f8 {
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compatible = "ns16550";
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reg = <0x000003f8 0x100>;
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io-mapped;
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clock-frequency = <1843200>;
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interrupts = <4 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
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interrupt-parent = <&intc>;
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reg-shift = <0>;
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status = "disabled";
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};
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uart1: uart@2f8 {
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compatible = "ns16550";
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reg = <0x000002f8 0x100>;
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io-mapped;
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clock-frequency = <1843200>;
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interrupts = <3 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
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interrupt-parent = <&intc>;
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reg-shift = <0>;
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status = "disabled";
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};
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hpet: hpet@fed00000 {
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compatible = "intel,hpet";
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reg = <0xfed00000 0x400>;
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interrupts = <2 IRQ_TYPE_FIXED_EDGE_RISING 4>;
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interrupt-parent = <&intc>;
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status = "disabled";
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};
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rtc: counter: rtc@70 {
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compatible = "motorola,mc146818";
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reg = <0x70 0x0D 0x71 0x0D>;
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interrupts = <8 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
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interrupt-parent = <&intc>;
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alarms-count = <1>;
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status = "okay";
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};
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};
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};
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