76 lines
2.0 KiB
C
76 lines
2.0 KiB
C
/*
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* Copyright (c) 2019 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_IPM_IPM_MHU_H_
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#define ZEPHYR_DRIVERS_IPM_IPM_MHU_H_
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#include <kernel.h>
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#include <drivers/ipm.h>
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#include <device.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define IPM_MHU_MAX_DATA_SIZE 1
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#define IPM_MHU_MAX_ID_VAL 0
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#define SSE_200_CPU_ID_UNIT_OFFSET ((0x1F000UL))
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#define SSE_200_DEVICE_BASE_REG_MSK (0xF0000000UL)
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/* SSE 200 MHU register map structure */
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struct ipm_mhu_reg_map_t {
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/* (R/ ) CPU 0 Interrupt Status Register */
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volatile u32_t cpu0intr_stat;
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volatile u32_t cpu0intr_set; /* ( /W) CPU 0 Interrupt Set Register */
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volatile u32_t cpu0intr_clr; /* ( /W) CPU 0 Interrupt Clear Register */
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volatile u32_t reserved0;
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/* (R/ ) CPU 1 Interrupt Status Register */
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volatile u32_t cpu1intr_stat;
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volatile u32_t cpu1intr_set; /* ( /W) CPU 1 Interrupt Set Register */
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volatile u32_t cpu1intr_clr; /* ( /W) CPU 1 Interrupt Clear Register */
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volatile u32_t reserved1[1004];
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volatile u32_t pidr4; /* ( /W) Peripheral ID 4 */
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volatile u32_t reserved2[3];
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volatile u32_t pidr0; /* ( /W) Peripheral ID 0 */
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volatile u32_t pidr1; /* ( /W) Peripheral ID 1 */
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volatile u32_t pidr2; /* ( /W) Peripheral ID 2 */
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volatile u32_t pidr3; /* ( /W) Peripheral ID 3 */
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volatile u32_t cidr0; /* ( /W) Component ID 0 */
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volatile u32_t cidr1; /* ( /W) Component ID 1 */
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volatile u32_t cidr2; /* ( /W) Component ID 2 */
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volatile u32_t cidr3; /* ( /W) Component ID 3 */
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};
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/* MHU enumeration types */
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enum ipm_mhu_error_t {
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IPM_MHU_ERR_NONE = 0, /* No error */
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IPM_MHU_ERR_INVALID_ARG, /* Invalid argument */
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};
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/* MHU enumeration types */
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enum ipm_mhu_cpu_id_t {
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IPM_MHU_CPU0 = 0,
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IPM_MHU_CPU1,
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IPM_MHU_CPU_MAX,
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};
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struct ipm_mhu_device_config {
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u8_t *base;
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void (*irq_config_func)(struct device *d);
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};
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/* Device data structure */
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struct ipm_mhu_data {
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ipm_callback_t callback;
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void *callback_ctx;
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /* ZEPHYR_DRIVERS_IPM_IPM_MHU_H_ */
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