114 lines
2.3 KiB
Plaintext
114 lines
2.3 KiB
Plaintext
/*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Copyright (C) 2021-2022, Intel Corporation
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*
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*/
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#include <arm64/armv8-a.dtsi>
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#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
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#include <zephyr/dt-bindings/clock/intel_socfpga_clock.h>
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#include <mem.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells= <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0>;
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <0x1>;
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};
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cpu2: cpu@2 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <0x2>;
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};
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cpu3: cpu@3 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <0x3>;
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};
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};
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gic: interrupt-controller@fffc1000 {
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compatible = "arm,gic";
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reg = <0xfffc1000 0x1000>,
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<0xfffc2000 0x2000>;
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interrupt-controller;
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#interrupt-cells = <4>;
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status = "okay";
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};
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arch_timer: timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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};
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sysmgr: sysmgr@ffd12000 {
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compatible = "syscon";
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reg = <0xffd12000 0x1000>;
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};
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clock: clock@ffd10000 {
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compatible = "intel,agilex-clock";
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reg = <0xffd10000 0x1000>;
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#clock-cells = <1>;
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};
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/*
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* This qspi setting included
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* The QSPI controller register and
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* The QSPI data register
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* QSPI REG <0xff8d2000 0x100>
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* QSPI DATA <0xff900000 0x100000>
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*/
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qspi: qspi@ff8d2000 {
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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compatible = "cdns,qspi-nor";
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reg = <0xff8d2000 0x100>,
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<0xff900000 0x100000>;
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reg-names = "qspi_reg", "qspi_data";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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clock-frequency = <50000000>;
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status = "disabled";
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};
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mem0: memory@10000000 {
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device_type = "memory";
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reg = <0x10000000 0x200000>;
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};
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uart0: uart@ffc02000 {
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compatible = "ns16550";
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reg-shift = <2>;
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reg = <0xffc02000 0x100>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0";
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clocks = <&clock INTEL_SOCFPGA_CLOCK_UART>;
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status = "disabled";
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};
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};
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