134 lines
3.4 KiB
C
134 lines
3.4 KiB
C
/*
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* Copyright (c) 2019-2020 Cobham Gaisler AB
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* This driver uses two independent GPTIMER subtimers in the following way:
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* - subtimer 0 generates periodic interrupts and the ISR announces ticks.
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* - subtimer 1 is used as up-counter.
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*/
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#define DT_DRV_COMPAT gaisler_gptimer
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#include <zephyr/device.h>
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#include <zephyr/drivers/timer/system_timer.h>
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#include <zephyr/sys_clock.h>
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/* GPTIMER subtimer increments each microsecond. */
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#define PRESCALER (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / 1000000)
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/* GPTIMER Timer instance */
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struct gptimer_timer_regs {
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uint32_t counter;
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uint32_t reload;
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uint32_t ctrl;
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uint32_t latch;
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};
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/* A GPTIMER can have maximum of 7 subtimers. */
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#define GPTIMER_MAX_SUBTIMERS 7
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/* GPTIMER common registers */
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struct gptimer_regs {
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uint32_t scaler_value;
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uint32_t scaler_reload;
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uint32_t cfg;
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uint32_t latch_cfg;
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struct gptimer_timer_regs timer[GPTIMER_MAX_SUBTIMERS];
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};
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#define GPTIMER_CTRL_WN (1 << 7)
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#define GPTIMER_CTRL_IP (1 << 4)
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#define GPTIMER_CTRL_IE (1 << 3)
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#define GPTIMER_CTRL_LD (1 << 2)
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#define GPTIMER_CTRL_RS (1 << 1)
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#define GPTIMER_CTRL_EN (1 << 0)
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#define GPTIMER_CFG_EL (1 << 11)
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#define GPTIMER_CFG_DF (1 << 9)
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#define GPTIMER_CFG_SI (1 << 8)
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#define GPTIMER_CFG_IRQ (0x1f << 3)
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#define GPTIMER_CFG_TIMERS (7 << 0)
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static volatile struct gptimer_regs *get_regs(void)
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{
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return (struct gptimer_regs *) DT_INST_REG_ADDR(0);
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}
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static int get_timer_irq(void)
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{
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return DT_INST_IRQN(0);
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}
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static uint32_t gptimer_ctrl_clear_ip;
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static void timer_isr(const void *unused)
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{
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ARG_UNUSED(unused);
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volatile struct gptimer_regs *regs = get_regs();
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volatile struct gptimer_timer_regs *tmr = ®s->timer[0];
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uint32_t ctrl;
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ctrl = tmr->ctrl;
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if ((ctrl & GPTIMER_CTRL_IP) == 0) {
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return; /* interrupt not for us */
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}
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/* Clear pending */
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tmr->ctrl = GPTIMER_CTRL_IE | GPTIMER_CTRL_RS |
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GPTIMER_CTRL_EN | gptimer_ctrl_clear_ip;
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sys_clock_announce(1);
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}
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uint32_t sys_clock_elapsed(void)
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{
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return 0;
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}
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uint32_t sys_clock_cycle_get_32(void)
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{
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volatile struct gptimer_regs *regs = get_regs();
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volatile struct gptimer_timer_regs *tmr = ®s->timer[1];
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uint32_t counter = tmr->counter;
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return (0 - counter) * PRESCALER;
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}
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static void init_downcounter(volatile struct gptimer_timer_regs *tmr)
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{
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tmr->reload = 0xFFFFFFFF;
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tmr->ctrl = GPTIMER_CTRL_LD | GPTIMER_CTRL_RS | GPTIMER_CTRL_EN;
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}
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static int sys_clock_driver_init(const struct device *dev)
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{
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ARG_UNUSED(dev);
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const int timer_interrupt = get_timer_irq();
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volatile struct gptimer_regs *regs = get_regs();
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volatile struct gptimer_timer_regs *tmr = ®s->timer[0];
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init_downcounter(®s->timer[1]);
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/* Stop timer and probe how CTRL_IP is cleared (write 1 or 0). */
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tmr->ctrl = GPTIMER_CTRL_IP;
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if ((tmr->ctrl & GPTIMER_CTRL_IP) == 0) {
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/* IP bit is cleared by setting it to 1. */
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gptimer_ctrl_clear_ip = GPTIMER_CTRL_IP;
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}
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/* Configure timer scaler for 1 MHz subtimer tick */
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regs->scaler_reload = PRESCALER - 1;
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tmr->reload = 1000000U / CONFIG_SYS_CLOCK_TICKS_PER_SEC - 1;
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tmr->ctrl = GPTIMER_CTRL_IE | GPTIMER_CTRL_LD | GPTIMER_CTRL_RS |
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GPTIMER_CTRL_EN;
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irq_connect_dynamic(timer_interrupt, 0, timer_isr, NULL, 0);
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irq_enable(timer_interrupt);
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return 0;
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}
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SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2,
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CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
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