63 lines
1.4 KiB
C
63 lines
1.4 KiB
C
/*
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* Copyright (c) 2019 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief System/hardware module for STM32H7 CM4 processor
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <soc.h>
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#include <stm32_ll_bus.h>
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#include <stm32_ll_cortex.h>
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#include <stm32_ll_pwr.h>
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#include <stm32_ll_rcc.h>
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#include <stm32_ll_system.h>
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#include "stm32_hsem.h"
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#include <cmsis_core.h>
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/**
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* @brief Perform basic hardware initialization at boot.
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*
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* This needs to be run from the very beginning.
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* So the init priority has to be 0 (zero).
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*
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* @return 0
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*/
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static int stm32h7_m4_init(void)
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{
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/* Enable ART Flash cache accelerator */
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LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_ART);
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LL_ART_SetBaseAddress(DT_REG_ADDR(DT_CHOSEN(zephyr_flash)));
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LL_ART_Enable();
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/* Enable hardware semaphore clock */
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LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_HSEM);
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/* In case CM4 has not been forced boot by CM7,
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* CM4 needs to wait until CM7 has setup clock configuration
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*/
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if (!LL_RCC_IsCM4BootForced()) {
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/*
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* Domain D2 is waiting for Cortex-M7 to perform
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* system initialization
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* (system clock config, external memory configuration.. ).
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* End of system initialization is reached when CM7 takes HSEM.
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*/
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while ((HSEM->RLR[CFG_HW_ENTRY_STOP_MODE_SEMID] & HSEM_R_LOCK)
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!= HSEM_R_LOCK) {
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;
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}
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}
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return 0;
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}
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SYS_INIT(stm32h7_m4_init, PRE_KERNEL_1, 0);
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