69 lines
1.8 KiB
C
69 lines
1.8 KiB
C
/*
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* Copyright 2022-2023 NXP
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/devicetree.h>
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#include "flexspi_clock_setup.h"
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#ifdef CONFIG_MEMC
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#include <fsl_flexspi.h>
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#include <fsl_clock.h>
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#endif
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#ifdef CONFIG_MEMC
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/**
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* @brief Set flexspi clock to given frequency
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*
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* This function differs from the above function in that it will not configure
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* the FlexSPI with a new MUX source, only change the divider. This function
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* is used by the clock control framework to set the clock frequency of
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* the FlexSPI
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*/
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int __ramfunc flexspi_clock_set_freq(uint32_t clock_name, uint32_t rate)
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{
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uint32_t root_rate;
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uint32_t divider;
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(void)clock_name; /* Not used by this function */
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/* Get the root clock rate: FlexSPI clock * divisor */
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root_rate = ((CLKCTL0->FLEXSPIFCLKDIV & CLKCTL0_FLEXSPIFCLKDIV_DIV_MASK) + 1) *
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CLOCK_GetFlexspiClkFreq();
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/* Select a divider based on root frequency.
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* if we can't get an exact divider, round down
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*/
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divider = ((root_rate + (rate - 1)) / rate) - 1;
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/* Cap divider to max value */
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divider = MIN(divider, CLKCTL0_FLEXSPIFCLKDIV_DIV_MASK);
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while (FLEXSPI_GetBusIdleStatus(FLEXSPI) == false) {
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/* Spin */
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}
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FLEXSPI_Enable(FLEXSPI, false);
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set_flexspi_clock(FLEXSPI, (CLKCTL0->FLEXSPIFCLKSEL &
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CLKCTL0_FLEXSPIFCLKSEL_SEL_MASK), (divider + 1));
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FLEXSPI_Enable(FLEXSPI, true);
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FLEXSPI_SoftwareReset(FLEXSPI);
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return 0;
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}
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#endif
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/**
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* @brief Set flexspi clock
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*/
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void __ramfunc set_flexspi_clock(FLEXSPI_Type *base, uint32_t src, uint32_t divider)
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{
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CLKCTL0->FLEXSPIFCLKSEL = CLKCTL0_FLEXSPIFCLKSEL_SEL(src);
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CLKCTL0->FLEXSPIFCLKDIV |=
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CLKCTL0_FLEXSPIFCLKDIV_RESET_MASK; /* Reset the divider counter */
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CLKCTL0->FLEXSPIFCLKDIV = CLKCTL0_FLEXSPIFCLKDIV_DIV(divider - 1);
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while ((CLKCTL0->FLEXSPIFCLKDIV) & CLKCTL0_FLEXSPIFCLKDIV_REQFLAG_MASK) {
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}
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}
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