398 lines
9.5 KiB
C
398 lines
9.5 KiB
C
/*
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* Copyright (c) 2019 Vestas Wind Systems A/S
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* Copyright (c) 2020 Innoseis BV
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* Copyright (c) 2023 Cruise LLC
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/device.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/drivers/adc.h>
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#include <zephyr/drivers/i2c.h>
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#include <zephyr/kernel.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/sys/byteorder.h>
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#include <zephyr/sys/util.h>
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#define ADC_CONTEXT_USES_KERNEL_TIMER 1
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#include "adc_context.h"
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#define DT_DRV_COMPAT ti_ads1112
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LOG_MODULE_REGISTER(ADS1112, CONFIG_ADC_LOG_LEVEL);
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#define ADS1112_CONFIG_GAIN(x) ((x)&BIT_MASK(2))
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#define ADS1112_CONFIG_DR(x) (((x)&BIT_MASK(2)) << 2)
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#define ADS1112_CONFIG_CM(x) (((x)&BIT_MASK(1)) << 4)
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#define ADS1112_CONFIG_MUX(x) (((x)&BIT_MASK(2)) << 5)
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#define ADS1112_CONFIG_MASK_READY BIT(7)
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#define ADS1112_DEFAULT_CONFIG 0x8C
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#define ADS1112_REF_INTERNAL 2048
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enum ads1112_reg {
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ADS1112_REG_OUTPUT = 0,
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ADS1112_REG_CONFIG = 1,
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};
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enum {
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ADS1112_CONFIG_MUX_DIFF_0_1 = 0,
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ADS1112_CONFIG_MUX_BOTH_2_3 = 1,
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ADS1112_CONFIG_MUX_SINGLE_0_3 = 2,
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ADS1112_CONFIG_MUX_SINGLE_1_3 = 3,
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};
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enum {
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ADS1112_CONFIG_DR_RATE_240_RES_12 = 0,
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ADS1112_CONFIG_DR_RATE_60_RES_14 = 1,
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ADS1112_CONFIG_DR_RATE_30_RES_15 = 2,
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ADS1112_CONFIG_DR_RATE_15_RES_16 = 3,
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ADS1112_CONFIG_DR_DEFAULT = ADS1112_CONFIG_DR_RATE_15_RES_16,
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};
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enum {
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ADS1112_CONFIG_GAIN_1 = 0,
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ADS1112_CONFIG_GAIN_2 = 1,
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ADS1112_CONFIG_GAIN_4 = 2,
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ADS1112_CONFIG_GAIN_8 = 3,
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};
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enum {
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ADS1112_CONFIG_CM_SINGLE = 0,
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ADS1112_CONFIG_CM_CONTINUOUS = 1,
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};
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struct ads1112_config {
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const struct i2c_dt_spec bus;
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};
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struct ads1112_data {
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struct adc_context ctx;
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k_timeout_t ready_time;
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struct k_sem acq_sem;
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int16_t *buffer;
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int16_t *buffer_ptr;
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bool differential;
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};
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static int ads1112_read_reg(const struct device *dev, enum ads1112_reg reg_addr, uint8_t *reg_val)
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{
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const struct ads1112_config *config = dev->config;
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uint8_t buf[3] = {0};
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int rc = i2c_read_dt(&config->bus, buf, sizeof(buf));
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if (reg_addr == ADS1112_REG_OUTPUT) {
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reg_val[0] = buf[0];
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reg_val[1] = buf[1];
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} else {
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reg_val[0] = buf[2];
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}
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return rc;
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}
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static int ads1112_write_reg(const struct device *dev, uint8_t reg)
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{
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uint8_t msg[1] = {reg};
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const struct ads1112_config *config = dev->config;
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/* It's only possible to write the config register, so the ADS1112
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* assumes all writes are going to that register and omits the register
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* parameter from write transactions
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*/
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return i2c_write_dt(&config->bus, msg, sizeof(msg));
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}
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static inline int ads1112_acq_time_to_dr(const struct device *dev, uint16_t acq_time)
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{
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struct ads1112_data *data = dev->data;
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int odr = -EINVAL;
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uint16_t acq_value = ADC_ACQ_TIME_VALUE(acq_time);
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uint32_t ready_time_us = 0;
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if (acq_time == ADC_ACQ_TIME_DEFAULT) {
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acq_value = ADS1112_CONFIG_DR_DEFAULT;
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} else if (ADC_ACQ_TIME_UNIT(acq_time) != ADC_ACQ_TIME_TICKS) {
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return -EINVAL;
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}
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switch (acq_value) {
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case ADS1112_CONFIG_DR_RATE_15_RES_16:
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odr = ADS1112_CONFIG_DR_RATE_15_RES_16;
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ready_time_us = (1000 * 1000) / 15;
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break;
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case ADS1112_CONFIG_DR_RATE_30_RES_15:
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odr = ADS1112_CONFIG_DR_RATE_30_RES_15;
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ready_time_us = (1000 * 1000) / 30;
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break;
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case ADS1112_CONFIG_DR_RATE_60_RES_14:
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odr = ADS1112_CONFIG_DR_RATE_60_RES_14;
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ready_time_us = (1000 * 1000) / 60;
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break;
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case ADS1112_CONFIG_DR_RATE_240_RES_12:
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odr = ADS1112_CONFIG_DR_RATE_240_RES_12;
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ready_time_us = (1000 * 1000) / 240;
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break;
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default:
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break;
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}
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/* Add some additional time to ensure that the data is truly ready,
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* as chips in this family often require some additional time beyond
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* the listed times
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*/
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data->ready_time = K_USEC(ready_time_us + 10);
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return odr;
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}
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static int ads1112_wait_data_ready(const struct device *dev)
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{
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int rc;
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struct ads1112_data *data = dev->data;
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k_sleep(data->ready_time);
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uint8_t status = 0;
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rc = ads1112_read_reg(dev, ADS1112_REG_CONFIG, &status);
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if (rc != 0) {
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return rc;
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}
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while ((status & ADS1112_CONFIG_MASK_READY) == 0) {
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k_sleep(K_USEC(100));
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rc = ads1112_read_reg(dev, ADS1112_REG_CONFIG, &status);
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if (rc != 0) {
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return rc;
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}
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}
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return 0;
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}
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static int ads1112_read_sample(const struct device *dev, uint16_t *buff)
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{
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int res;
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uint8_t sample[2] = {0};
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const struct ads1112_config *config = dev->config;
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res = ads1112_read_reg(dev, ADS1112_REG_OUTPUT, sample);
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buff[0] = sys_get_be16(sample);
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return res;
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}
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static int ads1112_channel_setup(const struct device *dev,
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const struct adc_channel_cfg *channel_cfg)
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{
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struct ads1112_data *data = dev->data;
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uint8_t config = 0;
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int dr = 0;
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if (channel_cfg->channel_id != 0) {
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return -EINVAL;
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}
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if (channel_cfg->differential) {
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if (channel_cfg->input_positive == 0 && channel_cfg->input_negative == 1) {
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config |= ADS1112_CONFIG_MUX(ADS1112_CONFIG_MUX_DIFF_0_1);
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} else if (channel_cfg->input_positive == 2 && channel_cfg->input_negative == 3) {
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config |= ADS1112_CONFIG_MUX(ADS1112_CONFIG_MUX_BOTH_2_3);
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} else {
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return -EINVAL;
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}
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} else {
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if (channel_cfg->input_positive == 0) {
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config |= ADS1112_CONFIG_MUX(ADS1112_CONFIG_MUX_SINGLE_0_3);
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} else if (channel_cfg->input_positive == 1) {
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config |= ADS1112_CONFIG_MUX(ADS1112_CONFIG_MUX_SINGLE_1_3);
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} else if (channel_cfg->input_positive == 2) {
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config |= ADS1112_CONFIG_MUX(ADS1112_CONFIG_MUX_BOTH_2_3);
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} else {
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return -EINVAL;
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}
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}
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data->differential = channel_cfg->differential;
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dr = ads1112_acq_time_to_dr(dev, channel_cfg->acquisition_time);
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if (dr < 0) {
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return dr;
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}
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config |= ADS1112_CONFIG_DR(dr);
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switch (channel_cfg->gain) {
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case ADC_GAIN_1:
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config |= ADS1112_CONFIG_GAIN(ADS1112_CONFIG_GAIN_1);
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break;
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case ADC_GAIN_2:
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config |= ADS1112_CONFIG_GAIN(ADS1112_CONFIG_GAIN_2);
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break;
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case ADC_GAIN_3:
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config |= ADS1112_CONFIG_GAIN(ADS1112_CONFIG_GAIN_4);
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break;
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case ADC_GAIN_4:
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config |= ADS1112_CONFIG_GAIN(ADS1112_CONFIG_GAIN_8);
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break;
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default:
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return -EINVAL;
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}
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config |= ADS1112_CONFIG_CM(ADS1112_CONFIG_CM_SINGLE); /* Only single shot supported */
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return ads1112_write_reg(dev, config);
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}
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static int ads1112_validate_buffer_size(const struct adc_sequence *sequence)
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{
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size_t needed = sizeof(int16_t);
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if (sequence->options) {
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needed *= (1 + sequence->options->extra_samplings);
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}
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if (sequence->buffer_size < needed) {
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LOG_ERR("Insufficient buffer %i < %i", sequence->buffer_size, needed);
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return -ENOMEM;
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}
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return 0;
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}
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static int ads1112_validate_sequence(const struct device *dev, const struct adc_sequence *sequence)
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{
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const struct ads1112_data *data = dev->data;
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if (sequence->channels != BIT(0)) {
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LOG_ERR("Invalid Channel 0x%x", sequence->channels);
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return -EINVAL;
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}
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if (sequence->oversampling) {
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LOG_ERR("Oversampling not supported");
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return -EINVAL;
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}
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return ads1112_validate_buffer_size(sequence);
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}
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static void adc_context_update_buffer_pointer(struct adc_context *ctx, bool repeat_sampling)
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{
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struct ads1112_data *data = CONTAINER_OF(ctx, struct ads1112_data, ctx);
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if (repeat_sampling) {
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data->buffer = data->buffer_ptr;
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}
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}
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static void adc_context_start_sampling(struct adc_context *ctx)
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{
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struct ads1112_data *data = CONTAINER_OF(ctx, struct ads1112_data, ctx);
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data->buffer_ptr = data->buffer;
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k_sem_give(&data->acq_sem);
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}
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static int ads1112_adc_start_read(const struct device *dev, const struct adc_sequence *sequence,
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bool wait)
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{
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int rc = 0;
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struct ads1112_data *data = dev->data;
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rc = ads1112_validate_sequence(dev, sequence);
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if (rc != 0) {
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return rc;
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}
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data->buffer = sequence->buffer;
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adc_context_start_read(&data->ctx, sequence);
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if (wait) {
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rc = adc_context_wait_for_completion(&data->ctx);
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}
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return rc;
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}
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static int ads1112_adc_perform_read(const struct device *dev)
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{
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int rc;
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struct ads1112_data *data = dev->data;
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k_sem_take(&data->acq_sem, K_FOREVER);
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rc = ads1112_wait_data_ready(dev);
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if (rc != 0) {
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adc_context_complete(&data->ctx, rc);
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return rc;
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}
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rc = ads1112_read_sample(dev, data->buffer);
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if (rc != 0) {
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adc_context_complete(&data->ctx, rc);
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return rc;
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}
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data->buffer++;
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adc_context_on_sampling_done(&data->ctx, dev);
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return rc;
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}
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static int ads1112_read(const struct device *dev, const struct adc_sequence *sequence)
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{
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int rc;
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struct ads1112_data *data = dev->data;
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adc_context_lock(&data->ctx, false, NULL);
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rc = ads1112_adc_start_read(dev, sequence, false);
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while (rc == 0 && k_sem_take(&data->ctx.sync, K_NO_WAIT) != 0) {
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rc = ads1112_adc_perform_read(dev);
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}
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adc_context_release(&data->ctx, rc);
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return rc;
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}
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static int ads1112_init(const struct device *dev)
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{
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int rc = 0;
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uint8_t status;
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const struct ads1112_config *config = dev->config;
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struct ads1112_data *data = dev->data;
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adc_context_init(&data->ctx);
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k_sem_init(&data->acq_sem, 0, 1);
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if (!device_is_ready(config->bus.bus)) {
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return -ENODEV;
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}
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rc = ads1112_write_reg(dev, ADS1112_DEFAULT_CONFIG);
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if (rc) {
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LOG_ERR("Could not set default config 0x%x", ADS1112_DEFAULT_CONFIG);
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return rc;
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}
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adc_context_unlock_unconditionally(&data->ctx);
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return rc;
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}
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static const struct adc_driver_api api = {
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.channel_setup = ads1112_channel_setup,
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.read = ads1112_read,
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.ref_internal = ADS1112_REF_INTERNAL,
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};
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#define ADC_ADS1112_INST_DEFINE(n) \
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static const struct ads1112_config config_##n = {.bus = I2C_DT_SPEC_INST_GET(n)}; \
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static struct ads1112_data data_##n; \
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DEVICE_DT_INST_DEFINE(n, ads1112_init, NULL, &data_##n, &config_##n, POST_KERNEL, \
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CONFIG_ADC_INIT_PRIORITY, &api);
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DT_INST_FOREACH_STATUS_OKAY(ADC_ADS1112_INST_DEFINE);
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