149 lines
5.4 KiB
C
149 lines
5.4 KiB
C
/*
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* Copyright (c) 2022 Intel Corporation
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*
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* Intel I/O Controller Hub (ICH) later renamed to Intel Platform Controller
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* Hub (PCH) SMbus driver.
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*
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* PCH provides SMBus 2.0 - compliant Host Controller.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_SMBUS_PCH_H_
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#define ZEPHYR_DRIVERS_SMBUS_PCH_H_
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/* PCI Configuration Space registers */
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/* Host Configuration (HCFG) - Offset 40h, 8 bits */
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#define PCH_SMBUS_HCFG 0x10
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#define PCH_SMBUS_HCFG_HST_EN BIT(0) /* Enable SMBus controller */
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/* PCH SMBus I/O and Memory Mapped registers */
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/* Host Status Register Address (HSTS) */
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#define PCH_SMBUS_HSTS 0x00
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#define PCH_SMBUS_HSTS_HOST_BUSY BIT(0) /* Host Busy */
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#define PCH_SMBUS_HSTS_INTERRUPT BIT(1) /* Interrupt */
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#define PCH_SMBUS_HSTS_DEV_ERROR BIT(2) /* Device Error */
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#define PCH_SMBUS_HSTS_BUS_ERROR BIT(3) /* Bus Error */
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#define PCH_SMBUS_HSTS_FAILED BIT(4) /* Failed */
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#define PCH_SMBUS_HSTS_SMB_ALERT BIT(5) /* SMB Alert */
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#define PCH_SMBUS_HSTS_INUSE BIT(6) /* In Use */
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#define PCH_SMBUS_HSTS_BYTE_DONE BIT(7) /* Byte Done */
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#define PCH_SMBUS_HSTS_ERROR (PCH_SMBUS_HSTS_DEV_ERROR | \
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PCH_SMBUS_HSTS_BUS_ERROR | \
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PCH_SMBUS_HSTS_FAILED)
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/* Host Control Register (HCTL) */
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#define PCH_SMBUS_HCTL 0x02 /* Host Control */
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#define PCH_SMBUS_HCTL_INTR_EN BIT(0) /* INT Enable */
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#define PCH_SMBUS_HCTL_KILL BIT(1) /* Kill current trans */
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#define PCH_SMBUS_HCTL_CMD GENMASK(4, 2) /* Command */
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/* SMBUS Commands */
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#define PCH_SMBUS_HCTL_CMD_QUICK (0 << 2) /* Quick cmd*/
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#define PCH_SMBUS_HCTL_CMD_BYTE (1 << 2) /* Byte cmd */
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#define PCH_SMBUS_HCTL_CMD_BYTE_DATA (2 << 2) /* Byte Data cmd */
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#define PCH_SMBUS_HCTL_CMD_WORD_DATA (3 << 2) /* Word Data cmd */
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#define PCH_SMBUS_HCTL_CMD_PROC_CALL (4 << 2) /* Process Call cmd */
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#define PCH_SMBUS_HCTL_CMD_BLOCK (5 << 2) /* Block cmd */
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#define PCH_SMBUS_HCTL_CMD_I2C_READ (6 << 2) /* I2C Read cmd */
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#define PCH_SMBUS_HCTL_CMD_BLOCK_PROC (7 << 2) /* Block Process cmd */
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#define PCH_SMBUS_HCTL_CMD_SET(cmd) (cmd << 2)
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#define PCH_SMBUS_HCTL_CMD_GET(val) (val & PCH_SMBUS_HCTL_CMD)
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#define PCH_SMBUS_HCTL_LAST_BYTE BIT(5) /* Last byte block op */
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#define PCH_SMBUS_HCTL_START BIT(6) /* Start SMBUS cmd */
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#define PCH_SMBUS_HCTL_PEC_EN BIT(7) /* Enable PEC */
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/* Host Command Register (HCMD) */
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#define PCH_SMBUS_HCMD 0x03
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/* Transmit Slave Address Register (TSA) */
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#define PCH_SMBUS_TSA 0x04
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#define PCH_SMBUS_TSA_RW BIT(0) /* Direction */
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#define PCH_SMBUS_TSA_ADDR_MASK GENMASK(7, 1) /* Address mask */
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/* Set 7-bit address */
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#define PCH_SMBUS_TSA_ADDR_SET(addr) (((addr) & BIT_MASK(7)) << 1)
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/* Get Peripheral address from register value */
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#define PCH_SMBUS_TSA_ADDR_GET(reg) ((reg >> 1) & BIT_MASK(7))
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/* Data 0 Register (HD0) */
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#define PCH_SMBUS_HD0 0x05 /* Data 0 / Count */
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/* Data 1 Register (HD1) */
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#define PCH_SMBUS_HD1 0x06 /* Data 1 */
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/* Host Block Data (HBD) */
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#define PCH_SMBUS_HBD 0x07 /* Host block data */
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/* Packet Error Check Data Register (PEC) */
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#define PCH_SMBUS_PEC 0x08 /* PEC data */
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/* Receive Slave Address Register (RSA) */
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#define PCH_SMBUS_RSA 0x09 /* Receive slave addr */
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/* Slave Data Register (SD) (16 bits) */
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#define PCH_SMBUS_SD 0x0a /* Slave data */
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/* Auxiliary Status (AUXS) */
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#define PCH_SMBUS_AUXS 0x0c /* Auxiliary Status */
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#define PCH_SMBUS_AUXS_CRC_ERROR BIT(0) /* CRC error */
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/* Auxiliary Control (AUXC) */
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#define PCH_SMBUS_AUXC 0x0d /* Auxiliary Control */
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#define PCH_SMBUS_AUXC_AAC BIT(0) /* Auto append CRC */
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#define PCH_SMBUS_AUXC_EN_32BUF BIT(1) /* Enable 32-byte buf */
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/* SMLink Pin Control Register (SMLC) */
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#define PCH_SMBUS_SMLC 0x0e /* SMLink pin control */
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/* SMBus Pin control Register (SMBC) */
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#define PCH_SMBUS_SMBC 0x0f /* SMBus pin control */
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#define PCH_SMBUS_SMBC_CLK_CUR_STS BIT(0) /* SMBCLK pin status */
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#define PCH_SMBUS_SMBC_DATA_CUR_STS BIT(1) /* SMBDATA pin status */
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#define PCH_SMBUS_SMBC_CLK_CTL BIT(2) /* SMBCLK pin CTL */
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/* Slave Status Register (SSTS) */
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#define PCH_SMBUS_SSTS 0x10 /* Slave Status */
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#define PCH_SMBUS_SSTS_HNS BIT(0) /* Host Notify Status */
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/* Slave Command Register (SCMD) */
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#define PCH_SMBUS_SCMD 0x11 /* Slave Command */
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#define PCH_SMBUS_SCMD_HNI_EN BIT(0) /* Host Notify INT En */
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#define PCH_SMBUS_SCMD_HNW_EN BIT(1) /* Host Notify Wake */
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#define PCH_SMBUS_SCMD_SMBALERT_DIS BIT(2) /* Disable Smbalert */
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/* Notify Device Address Register (NDA) */
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#define PCH_SMBUS_NDA 0x14 /* Notify Device addr */
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/* Notify Data Low Byte Register (NDLB) */
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#define PCH_SMBUS_NDLB 0x16 /* Notify Data low */
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/* Notify Data High Byte Register (NDHB) */
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#define PCH_SMBUS_NDHB 0x17 /* Notify Data high */
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/* Debug helpers */
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#if CONFIG_SMBUS_LOG_LEVEL >= LOG_LEVEL_DBG
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/* Dump HSTS register using define to show calling function */
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#define pch_dump_register_hsts(reg) \
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LOG_DBG("HSTS: 0x%02x: %s%s%s%s%s%s%s%s", reg, \
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reg & PCH_SMBUS_HSTS_HOST_BUSY ? "[Host Busy] " : "", \
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reg & PCH_SMBUS_HSTS_INTERRUPT ? "[Interrupt] " : "", \
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reg & PCH_SMBUS_HSTS_DEV_ERROR ? "[Device Error] " : "",\
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reg & PCH_SMBUS_HSTS_BUS_ERROR ? "[Bus Error] " : "", \
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reg & PCH_SMBUS_HSTS_FAILED ? "[Failed] " : "", \
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reg & PCH_SMBUS_HSTS_SMB_ALERT ? "[SMBALERT] " : "", \
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reg & PCH_SMBUS_HSTS_BYTE_DONE ? "[Byte Done] " : "", \
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reg & PCH_SMBUS_HSTS_INUSE ? "[In USE] " : "");
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#else
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#define pch_dump_register_hsts(reg)
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#endif
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#endif /* ZEPHYR_DRIVERS_SMBUS_PCH_H_ */
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