175 lines
3.8 KiB
C
175 lines
3.8 KiB
C
/*
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* Copyright (c) 2018 Alexander Wachter
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <soc.h>
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#include <stm32_ll_utils.h>
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#include <stm32_ll_rcc.h>
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#if defined(CONFIG_SOC_SERIES_STM32H5X)
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#include <stm32_ll_icache.h>
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#endif /* CONFIG_SOC_SERIES_STM32H5X */
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#include <stm32_ll_pwr.h>
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#include <zephyr/drivers/hwinfo.h>
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#include <string.h>
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#include <zephyr/sys/byteorder.h>
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struct stm32_uid {
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uint32_t id[3];
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};
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ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length)
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{
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struct stm32_uid dev_id;
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#if defined(CONFIG_SOC_SERIES_STM32H5X)
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LL_ICACHE_Disable();
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#endif /* CONFIG_SOC_SERIES_STM32H5X */
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dev_id.id[0] = sys_cpu_to_be32(LL_GetUID_Word2());
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dev_id.id[1] = sys_cpu_to_be32(LL_GetUID_Word1());
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dev_id.id[2] = sys_cpu_to_be32(LL_GetUID_Word0());
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#if defined(CONFIG_SOC_SERIES_STM32H5X)
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LL_ICACHE_Enable();
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#endif /* CONFIG_SOC_SERIES_STM32H5X */
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if (length > sizeof(dev_id.id)) {
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length = sizeof(dev_id.id);
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}
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memcpy(buffer, dev_id.id, length);
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return length;
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}
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int z_impl_hwinfo_get_reset_cause(uint32_t *cause)
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{
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uint32_t flags = 0;
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#if defined(RCC_FLAG_SFTRST)
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if (LL_RCC_IsActiveFlag_SFTRST()) {
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flags |= RESET_SOFTWARE;
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}
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#endif
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#if defined(RCC_FLAG_PINRST)
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if (LL_RCC_IsActiveFlag_PINRST()) {
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flags |= RESET_PIN;
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}
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#endif
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#if defined(RCC_FLAG_IWDGRST)
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if (LL_RCC_IsActiveFlag_IWDGRST()) {
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flags |= RESET_WATCHDOG;
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}
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#endif
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#if defined(RCC_RSR_IWDG1RSTF)
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if (LL_RCC_IsActiveFlag_IWDG1RST()) {
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flags |= RESET_WATCHDOG;
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}
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#endif
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#if defined(RCC_RSR_IWDG2RSTF)
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if (LL_RCC_IsActiveFlag_IWDG2RST()) {
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flags |= RESET_WATCHDOG;
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}
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#endif
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#if defined(RCC_FLAG_WWDGRST)
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if (LL_RCC_IsActiveFlag_WWDGRST()) {
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flags |= RESET_WATCHDOG;
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}
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#endif
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#if defined(RCC_RSR_WWDG1RSTF)
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if (LL_RCC_IsActiveFlag_WWDG1RST()) {
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flags |= RESET_WATCHDOG;
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}
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#endif
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#if defined(RCC_RSR_WWDG2RSTF)
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if (LL_RCC_IsActiveFlag_WWDG2RST()) {
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flags |= RESET_WATCHDOG;
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}
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#endif
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#if defined(RCC_FLAG_FWRST)
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if (LL_RCC_IsActiveFlag_FWRST()) {
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flags |= RESET_SECURITY;
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}
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#endif
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#if defined(RCC_FLAG_BORRST)
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if (LL_RCC_IsActiveFlag_BORRST()) {
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flags |= RESET_BROWNOUT;
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}
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#endif
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#if defined(RCC_FLAG_PWRRST)
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if (LL_RCC_IsActiveFlag_PWRRST()) {
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flags |= RESET_POR;
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}
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#endif
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#if defined(RCC_FLAG_PORRST)
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if (LL_RCC_IsActiveFlag_PORRST()) {
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flags |= RESET_POR;
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}
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#endif
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#if defined(RCC_FLAG_LPWRRST)
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if (LL_RCC_IsActiveFlag_LPWRRST()) {
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flags |= RESET_LOW_POWER_WAKE;
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}
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#endif
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#if defined(CONFIG_SOC_SERIES_STM32H7X) && defined(CORE_CM4)
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if (LL_PWR_CPU2_IsActiveFlag_SB()) {
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flags |= RESET_LOW_POWER_WAKE;
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}
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#elif defined(CONFIG_SOC_SERIES_STM32H7X) && defined(CORE_CM7)
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if (LL_PWR_CPU_IsActiveFlag_SB()) {
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flags |= RESET_LOW_POWER_WAKE;
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}
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#elif defined(CONFIG_SOC_SERIES_STM32MP1X)
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if (LL_PWR_MCU_IsActiveFlag_SB()) {
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flags |= RESET_LOW_POWER_WAKE;
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}
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#elif defined(CONFIG_SOC_SERIES_STM32WLX) || defined(CONFIG_SOC_SERIES_STM32WBX)
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if (LL_PWR_IsActiveFlag_C1SB()) {
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flags |= RESET_LOW_POWER_WAKE;
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}
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#elif defined(PWR_FLAG_SB)
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if (LL_PWR_IsActiveFlag_SB()) {
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flags |= RESET_LOW_POWER_WAKE;
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}
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#endif /* PWR_FLAG_SB */
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*cause = flags;
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return 0;
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}
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int z_impl_hwinfo_clear_reset_cause(void)
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{
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LL_RCC_ClearResetFlags();
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#if defined(CONFIG_SOC_SERIES_STM32H7X) && defined(CORE_CM4)
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LL_PWR_ClearFlag_CPU2();
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#elif defined(CONFIG_SOC_SERIES_STM32H7X) && defined(CORE_CM7)
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LL_PWR_ClearFlag_CPU();
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#elif defined(CONFIG_SOC_SERIES_STM32MP1X)
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LL_PWR_ClearFlag_MCU();
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#elif defined(CONFIG_SOC_SERIES_STM32WLX) || defined(CONFIG_SOC_SERIES_STM32WBX)
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LL_PWR_ClearFlag_C1STOP_C1STB();
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#elif defined(PWR_FLAG_SB)
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LL_PWR_ClearFlag_SB();
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#endif /* PWR_FLAG_SB */
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return 0;
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}
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int z_impl_hwinfo_get_supported_reset_cause(uint32_t *supported)
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{
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*supported = (RESET_PIN
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| RESET_WATCHDOG
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| RESET_SOFTWARE
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| RESET_SECURITY
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| RESET_LOW_POWER_WAKE
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| RESET_POR
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| RESET_BROWNOUT);
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return 0;
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}
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