357 lines
8.7 KiB
C
357 lines
8.7 KiB
C
/*
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* Copyright (c) 2016 Linaro Limited.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT st_stm32_pwm
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#include <errno.h>
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#include <soc.h>
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#include <drivers/pwm.h>
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#include <device.h>
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#include <kernel.h>
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#include <init.h>
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#include <drivers/clock_control/stm32_clock_control.h>
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#include "pwm_stm32.h"
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#include <logging/log.h>
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LOG_MODULE_REGISTER(pwm_stm32);
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/* convenience defines */
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#define DEV_CFG(dev) \
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((const struct pwm_stm32_config * const)(dev)->config->config_info)
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#define DEV_DATA(dev) \
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((struct pwm_stm32_data * const)(dev)->driver_data)
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#define PWM_STRUCT(dev) \
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((TIM_TypeDef *)(DEV_CFG(dev))->pwm_base)
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#define CHANNEL_LENGTH 4
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static u32_t __get_tim_clk(u32_t bus_clk,
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clock_control_subsys_t *sub_system)
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{
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struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
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u32_t tim_clk, apb_psc;
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#if defined(CONFIG_SOC_SERIES_STM32H7X)
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if (pclken->bus == STM32_CLOCK_BUS_APB1) {
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apb_psc = CONFIG_CLOCK_STM32_D2PPRE1;
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} else {
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apb_psc = CONFIG_CLOCK_STM32_D2PPRE2;
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}
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/*
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* Depending on pre-scaler selection (TIMPRE), timer clock frequency
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* is defined as follows:
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*
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* - TIMPRE=0: If the APB prescaler (PPRE1, PPRE2) is configured to a
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* division factor of 1 then the timer clock equals to APB bus clock.
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* Otherwise the timer clock is set to twice the frequency of APB bus
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* clock.
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* - TIMPRE=1: If the APB prescaler (PPRE1, PPRE2) is configured to a
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* division factor of 1, 2 or 4, then the timer clock equals to HCLK.
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* Otherwise, the timer clock frequencies are set to four times to
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* the frequency of the APB domain.
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*/
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if (LL_RCC_GetTIMPrescaler() == LL_RCC_TIM_PRESCALER_TWICE) {
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if (apb_psc == 1U) {
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tim_clk = bus_clk;
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} else {
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tim_clk = bus_clk * 2U;
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}
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} else {
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if (apb_psc == 1U || apb_psc == 2U || apb_psc == 4U) {
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tim_clk = SystemCoreClock;
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} else {
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tim_clk = bus_clk * 4U;
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}
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}
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#else
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if (pclken->bus == STM32_CLOCK_BUS_APB1) {
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apb_psc = CONFIG_CLOCK_STM32_APB1_PRESCALER;
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}
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#if !defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_SOC_SERIES_STM32G0X)
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else {
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apb_psc = CONFIG_CLOCK_STM32_APB2_PRESCALER;
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}
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#endif
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/*
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* If the APB prescaler equals 1, the timer clock frequencies
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* are set to the same frequency as that of the APB domain.
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* Otherwise, they are set to twice (×2) the frequency of the
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* APB domain.
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*/
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if (apb_psc == 1U) {
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tim_clk = bus_clk;
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} else {
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tim_clk = bus_clk * 2U;
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}
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#endif
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return tim_clk;
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}
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/*
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* Set the period and pulse width for a PWM pin.
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*
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* Parameters
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* dev: Pointer to PWM device structure
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* pwm: PWM channel to set
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* period_cycles: Period (in timer count)
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* pulse_cycles: Pulse width (in timer count).
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*
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* return 0, or negative errno code
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*/
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static int pwm_stm32_pin_set(struct device *dev, u32_t pwm,
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u32_t period_cycles, u32_t pulse_cycles,
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pwm_flags_t flags)
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{
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struct pwm_stm32_data *data = DEV_DATA(dev);
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TIM_HandleTypeDef *TimerHandle = &data->hpwm;
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TIM_OC_InitTypeDef sConfig;
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u32_t channel;
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bool counter_32b;
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if (period_cycles == 0U || pulse_cycles > period_cycles) {
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return -EINVAL;
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}
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if (flags) {
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/* PWM polarity not supported (yet?) */
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return -ENOTSUP;
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}
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/* configure channel */
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channel = (pwm - 1)*CHANNEL_LENGTH;
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if (!IS_TIM_INSTANCE(PWM_STRUCT(dev)) ||
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!IS_TIM_CHANNELS(channel)) {
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return -ENOTSUP;
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}
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#ifdef CONFIG_SOC_SERIES_STM32F1X
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/* FIXME: IS_TIM_32B_COUNTER_INSTANCE not available on
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* SMT32F1 Cube HAL since all timer counters are 16 bits
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*/
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counter_32b = 0;
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#else
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counter_32b = IS_TIM_32B_COUNTER_INSTANCE(PWM_STRUCT(dev));
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#endif
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/*
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* The timer counts from 0 up to the value in the ARR register (16-bit).
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* Thus period_cycles cannot be greater than UINT16_MAX + 1.
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*/
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if (!counter_32b && (period_cycles > 0x10000)) {
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/* 16 bits counter does not support requested period
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* You might want to adapt PWM output clock to adjust
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* cycle durations to fit requested period into 16 bits
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* counter
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*/
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return -ENOTSUP;
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}
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/* Configure Timer IP */
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TimerHandle->Instance = PWM_STRUCT(dev);
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TimerHandle->Init.Prescaler = data->pwm_prescaler;
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TimerHandle->Init.ClockDivision = 0;
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TimerHandle->Init.CounterMode = TIM_COUNTERMODE_UP;
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TimerHandle->Init.RepetitionCounter = 0;
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/* Set period value */
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TimerHandle->Init.Period = period_cycles - 1;
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HAL_TIM_PWM_Init(TimerHandle);
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/* Configure PWM channel */
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sConfig.OCMode = TIM_OCMODE_PWM1;
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sConfig.OCPolarity = TIM_OCPOLARITY_HIGH;
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sConfig.OCFastMode = TIM_OCFAST_DISABLE;
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sConfig.OCNPolarity = TIM_OCNPOLARITY_HIGH;
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sConfig.OCNIdleState = TIM_OCNIDLESTATE_RESET;
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sConfig.OCIdleState = TIM_OCIDLESTATE_RESET;
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/* Set the pulse value */
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sConfig.Pulse = pulse_cycles;
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HAL_TIM_PWM_ConfigChannel(TimerHandle, &sConfig, channel);
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return HAL_TIM_PWM_Start(TimerHandle, channel);
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}
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/*
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* Get the clock rate (cycles per second) for a PWM pin.
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*
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* Parameters
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* dev: Pointer to PWM device structure
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* pwm: PWM port number
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* cycles: Pointer to the memory to store clock rate (cycles per second)
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*
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* return 0, or negative errno code
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*/
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static int pwm_stm32_get_cycles_per_sec(struct device *dev, u32_t pwm,
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u64_t *cycles)
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{
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const struct pwm_stm32_config *cfg = DEV_CFG(dev);
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struct pwm_stm32_data *data = DEV_DATA(dev);
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u32_t bus_clk, tim_clk;
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if (cycles == NULL) {
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return -EINVAL;
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}
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/* Timer clock depends on APB prescaler */
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if (clock_control_get_rate(data->clock,
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(clock_control_subsys_t *)&cfg->pclken, &bus_clk) < 0) {
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LOG_ERR("Failed call clock_control_get_rate");
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return -EIO;
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}
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tim_clk = __get_tim_clk(bus_clk,
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(clock_control_subsys_t *)&cfg->pclken);
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*cycles = (u64_t)(tim_clk / (data->pwm_prescaler + 1));
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return 0;
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}
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static const struct pwm_driver_api pwm_stm32_drv_api_funcs = {
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.pin_set = pwm_stm32_pin_set,
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.get_cycles_per_sec = pwm_stm32_get_cycles_per_sec,
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};
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static inline void __pwm_stm32_get_clock(struct device *dev)
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{
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struct pwm_stm32_data *data = DEV_DATA(dev);
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struct device *clk = device_get_binding(STM32_CLOCK_CONTROL_NAME);
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__ASSERT_NO_MSG(clk);
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data->clock = clk;
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}
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static int pwm_stm32_init(struct device *dev)
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{
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const struct pwm_stm32_config *config = DEV_CFG(dev);
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struct pwm_stm32_data *data = DEV_DATA(dev);
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__pwm_stm32_get_clock(dev);
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/* enable clock */
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if (clock_control_on(data->clock,
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(clock_control_subsys_t *)&config->pclken) != 0) {
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return -EIO;
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}
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return 0;
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}
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#define PWM_DEVICE_INIT_STM32(index) \
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static struct pwm_stm32_data pwm_stm32_dev_data_##index = { \
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/* Default case */ \
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.pwm_prescaler = DT_INST_PROP(index, st_prescaler),\
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}; \
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\
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static const struct pwm_stm32_config pwm_stm32_dev_cfg_##index = {\
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.pwm_base = DT_REG_ADDR(DT_INST(index, st_stm32_timers)),\
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.pclken = { \
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.bus = DT_CLOCKS_CELL(DT_INST(index, st_stm32_timers), bus),\
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.enr = DT_CLOCKS_CELL(DT_INST(index, st_stm32_timers), bits)\
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},\
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}; \
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\
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DEVICE_AND_API_INIT(pwm_stm32_##index, \
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DT_INST_LABEL(index), \
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pwm_stm32_init, \
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&pwm_stm32_dev_data_##index, \
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&pwm_stm32_dev_cfg_##index, \
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,\
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&pwm_stm32_drv_api_funcs)
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#if DT_HAS_DRV_INST(0)
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PWM_DEVICE_INIT_STM32(0);
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#endif /* DT_HAS_DRV_INST(0) */
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#if DT_HAS_DRV_INST(1)
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PWM_DEVICE_INIT_STM32(1);
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#endif /* DT_HAS_DRV_INST(1) */
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#if DT_HAS_DRV_INST(2)
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PWM_DEVICE_INIT_STM32(2);
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#endif /* DT_HAS_DRV_INST(2) */
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#if DT_HAS_DRV_INST(3)
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PWM_DEVICE_INIT_STM32(3);
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#endif /* DT_HAS_DRV_INST(3) */
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#if DT_HAS_DRV_INST(4)
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PWM_DEVICE_INIT_STM32(4);
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#endif /* DT_HAS_DRV_INST(4) */
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#if DT_HAS_DRV_INST(5)
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PWM_DEVICE_INIT_STM32(5);
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#endif /* DT_HAS_DRV_INST(5) */
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#if DT_HAS_DRV_INST(6)
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PWM_DEVICE_INIT_STM32(6);
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#endif /* DT_HAS_DRV_INST(6) */
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#if DT_HAS_DRV_INST(7)
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PWM_DEVICE_INIT_STM32(7);
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#endif /* DT_HAS_DRV_INST(7) */
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#if DT_HAS_DRV_INST(8)
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PWM_DEVICE_INIT_STM32(8);
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#endif /* DT_HAS_DRV_INST(8) */
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#if DT_HAS_DRV_INST(9)
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PWM_DEVICE_INIT_STM32(9);
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#endif /* DT_HAS_DRV_INST(9) */
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#if DT_HAS_DRV_INST(10)
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PWM_DEVICE_INIT_STM32(10);
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#endif /* DT_HAS_DRV_INST(10) */
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#if DT_HAS_DRV_INST(11)
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PWM_DEVICE_INIT_STM32(11);
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#endif /* DT_HAS_DRV_INST(11) */
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#if DT_HAS_DRV_INST(12)
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PWM_DEVICE_INIT_STM32(12);
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#endif /* DT_HAS_DRV_INST(12) */
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#if DT_HAS_DRV_INST(13)
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PWM_DEVICE_INIT_STM32(13);
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#endif /* DT_HAS_DRV_INST(13) */
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#if DT_HAS_DRV_INST(14)
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PWM_DEVICE_INIT_STM32(14);
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#endif /* DT_HAS_DRV_INST(14) */
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#if DT_HAS_DRV_INST(15)
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PWM_DEVICE_INIT_STM32(15);
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#endif /* DT_HAS_DRV_INST(15) */
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#if DT_HAS_DRV_INST(16)
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PWM_DEVICE_INIT_STM32(16);
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#endif /* DT_HAS_DRV_INST(16) */
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#if DT_HAS_DRV_INST(17)
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PWM_DEVICE_INIT_STM32(17);
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#endif /* DT_HAS_DRV_INST(17) */
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#if DT_HAS_DRV_INST(18)
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PWM_DEVICE_INIT_STM32(18);
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#endif /* DT_HAS_DRV_INST(18) */
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#if DT_HAS_DRV_INST(19)
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PWM_DEVICE_INIT_STM32(19);
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#endif /* DT_HAS_DRV_INST(19) */
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