120 lines
3.7 KiB
Plaintext
120 lines
3.7 KiB
Plaintext
# Kconfig - Multilevel interrupt configuration
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#
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# Copyright (c) 2017 Intel Corporation
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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config MULTI_LEVEL_INTERRUPTS
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bool "Multi-level Interrupts"
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default n
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depends on GEN_SW_ISR_TABLE
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help
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Multiple levels of interrupts are normally used to increase the
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number of addressable interrupts in a system. For e.g., if 2 levels
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of interrupts are used, the 2nd level controller would combine all
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interrupts routed to it into one line which then gets routed to one
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of the lines in 1st level interrupt controller.
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config MAX_IRQ_PER_AGGREGATOR
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int "Max IRQs per interrupt aggregator"
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default 0
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depends on MULTI_LEVEL_INTERRUPTS
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help
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This represents the max number of interrupts that an aggregator
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can map.
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config 2ND_LEVEL_INTERRUPTS
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bool "Second-level Interrupts"
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default n
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depends on MULTI_LEVEL_INTERRUPTS
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help
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Second level interrupts are used to increase the number of
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addressable interrupts in a system.
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config 2ND_LVL_ISR_TBL_OFFSET
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int "Offset in the SW ISR Table for 2nd level interrupt controller"
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default 0
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depends on MULTI_LEVEL_INTERRUPTS
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help
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This is the offset in the SW ISR table beginning where the ISRs for
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2nd level interrupts are located. This typically is allocated after
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allocating first level interrupts.
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config NUM_2ND_LEVEL_AGGREGATORS
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hex "Total Number of Second level Interrupt Aggregators"
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default 0
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depends on MULTI_LEVEL_INTERRUPTS
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help
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This is the number of second level interrupt aggregators present
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in the system. Each of these interrupt aggregators can typically
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map MAX_IRQ_PER_AGGREGATOR second level interrupts to one first
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level interrupt.
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config 2ND_LVL_INTR_00_OFFSET
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hex "Parent interrupt number to which controller_0 maps"
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default 0x00
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depends on 2ND_LEVEL_INTERRUPTS
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help
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This is the interrupt number in the first level to which
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controller_0 of second level maps.
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config 2ND_LVL_INTR_01_OFFSET
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hex "Parent interrupt number to which controller_1 maps"
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default 0x00
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depends on 2ND_LEVEL_INTERRUPTS
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help
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This is the interrupt number in the first level to which
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controller_1 of second level maps.
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config 2ND_LVL_INTR_02_OFFSET
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hex "Parent interrupt number to which controller_2 maps"
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default 0x00
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depends on 2ND_LEVEL_INTERRUPTS
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help
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This is the interrupt number in the first level to which
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controller_2 of second level maps.
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config 2ND_LVL_INTR_03_OFFSET
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hex "Parent interrupt number to which controller_3 maps"
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default 0x00
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depends on 2ND_LEVEL_INTERRUPTS
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help
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This is the interrupt number in the first level to which
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controller_3 of second level maps.
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config 3RD_LEVEL_INTERRUPTS
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bool "Third-level Interrupts"
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default n
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depends on 2ND_LEVEL_INTERRUPTS
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help
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Third level interrupts are used to increase the number of
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addressable interrupts in a system.
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config NUM_3RD_LEVEL_AGGREGATORS
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hex "Total Number of Third level Interrupt Aggregators"
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default 0
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depends on 3RD_LEVEL_INTERRUPTS
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help
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These are the number of third level interrupt aggregators present
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in the system. Each of these interrupt aggregators can typically
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map MAX_IRQ_PER_AGGREGATOR third level interrupts to one second
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level interrupt.
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config 3RD_LVL_ISR_TBL_OFFSET
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int "Offset in the SW ISR Table for 3rd level interrupt controller"
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default 0
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depends on 3RD_LEVEL_INTERRUPTS
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help
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This is the offset in the SW ISR table beginning where the ISRs for
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3rd level interrupts are located. This typically is allocated after
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allocating first and second level interrupts.
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config 3RD_LVL_INTR_00_OFFSET
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hex "Parent interrupt number to which controller_0 maps"
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default 0x00
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depends on 3RD_LEVEL_INTERRUPTS
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help
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This is the interrupt number in the second level to which
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controller_0 of third level maps.
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