1e6adba9ef
In a scenario where a platform harbours multiple interrupts to the extent the core cannot support it, an interrupt controller is added as an additional level of interrupt. It typically combines several sources of interrupt into one line that is then routed to the parent controller. Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com> |
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| .. | ||
| CMakeLists.txt | ||
| gen_isr_tables.py | ||
| isr_tables.c | ||
| timing_info_bench.c | ||