394 lines
11 KiB
Plaintext
394 lines
11 KiB
Plaintext
/*
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* Copyright (c) 2016 Cadence Design Systems, Inc.
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Linker command/script file
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*
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* Linker script for the Xtensa platform.
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*/
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#define _LINKER
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#define _ASMLANGUAGE
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#include <autoconf.h>
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#include <linker/sections.h>
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#include <linker/linker-defs.h>
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#include <linker/linker-tool.h>
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#define RAMABLE_REGION sram9_seg :sram9_phdr
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#define ROMABLE_REGION srom1_seg :srom1_phdr
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MEMORY
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{
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srom0_seg : org = 0x50000000, len = 0x2E0
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srom1_seg : org = 0x500002E0, len = 0xFFFD20
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sram0_seg : org = 0x60000000, len = 0x178
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sram1_seg : org = 0x60000178, len = 0x4
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sram2_seg : org = 0x6000017C, len = 0x1C
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sram3_seg : org = 0x60000198, len = 0x4
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sram4_seg : org = 0x6000019C, len = 0x1C
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sram5_seg : org = 0x600001B8, len = 0x4
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sram6_seg : org = 0x600001BC, len = 0x1C
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sram7_seg : org = 0x600001D8, len = 0x4
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sram8_seg : org = 0x600001DC, len = 0x1C
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sram9_seg : org = 0x600001F8, len = 0x3FFFE08
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#ifdef CONFIG_GEN_ISR_TABLES
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IDT_LIST : org = 0x4fffe000, len = 0x2000
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#endif
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}
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PHDRS
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{
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srom0_phdr PT_LOAD;
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srom1_phdr PT_LOAD;
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sram0_phdr PT_LOAD;
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sram1_phdr PT_LOAD;
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sram2_phdr PT_LOAD;
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sram3_phdr PT_LOAD;
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sram4_phdr PT_LOAD;
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sram5_phdr PT_LOAD;
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sram6_phdr PT_LOAD;
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sram7_phdr PT_LOAD;
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sram8_phdr PT_LOAD;
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sram9_phdr PT_LOAD;
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sram9_bss_phdr PT_LOAD;
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}
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/* Default entry point: */
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ENTRY(CONFIG_KERNEL_ENTRY)
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/* Memory boundary addresses: */
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_memmap_mem_srom_start = 0x50000000;
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_memmap_mem_srom_end = 0x51000000;
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_memmap_mem_sram_start = 0x60000000;
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_memmap_mem_sram_end = 0x64000000;
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/* Memory segment boundary addresses: */
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_memmap_seg_srom0_start = 0x50000000;
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_memmap_seg_srom0_max = 0x500002e0;
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_memmap_seg_srom1_start = 0x500002e0;
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_memmap_seg_srom1_max = 0x51000000;
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_memmap_seg_sram0_start = 0x60000000;
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_memmap_seg_sram0_max = 0x60000178;
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_memmap_seg_sram1_start = 0x60000178;
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_memmap_seg_sram1_max = 0x6000017c;
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_memmap_seg_sram2_start = 0x6000017c;
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_memmap_seg_sram2_max = 0x60000198;
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_memmap_seg_sram3_start = 0x60000198;
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_memmap_seg_sram3_max = 0x6000019c;
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_memmap_seg_sram4_start = 0x6000019c;
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_memmap_seg_sram4_max = 0x600001b8;
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_memmap_seg_sram5_start = 0x600001b8;
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_memmap_seg_sram5_max = 0x600001bc;
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_memmap_seg_sram6_start = 0x600001bc;
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_memmap_seg_sram6_max = 0x600001d8;
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_memmap_seg_sram7_start = 0x600001d8;
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_memmap_seg_sram7_max = 0x600001dc;
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_memmap_seg_sram8_start = 0x600001dc;
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_memmap_seg_sram8_max = 0x600001f8;
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_memmap_seg_sram9_start = 0x600001f8;
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_memmap_seg_sram9_max = 0x64000000;
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_rom_store_table = 0;
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PROVIDE(_memmap_vecbase_reset = 0x60000000);
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PROVIDE(_memmap_reset_vector = 0x50000000);
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/* Various memory-map dependent cache attribute settings: */
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_memmap_cacheattr_wb_base = 0x00004400;
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_memmap_cacheattr_wt_base = 0x00001100;
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_memmap_cacheattr_bp_base = 0x00002200;
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_memmap_cacheattr_unused_mask = 0xFFFF00FF;
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_memmap_cacheattr_wb_trapnull = 0x2222442F;
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_memmap_cacheattr_wba_trapnull = 0x2222442F;
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_memmap_cacheattr_wbna_trapnull = 0x2222552F;
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_memmap_cacheattr_wt_trapnull = 0x2222112F;
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_memmap_cacheattr_bp_trapnull = 0x2222222F;
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_memmap_cacheattr_wb_strict = 0xFFFF44FF;
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_memmap_cacheattr_wt_strict = 0xFFFF11FF;
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_memmap_cacheattr_bp_strict = 0xFFFF22FF;
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_memmap_cacheattr_wb_allvalid = 0x22224422;
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_memmap_cacheattr_wt_allvalid = 0x22221122;
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_memmap_cacheattr_bp_allvalid = 0x22222222;
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PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);
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SECTIONS
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{
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.ResetVector.text : ALIGN(4)
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{
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_image_rom_start = ABSOLUTE(.);
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_ResetVector_text_start = ABSOLUTE(.);
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KEEP (*(.ResetVector.text))
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_ResetVector_text_end = ABSOLUTE(.);
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_memmap_seg_srom0_end = ALIGN(0x8);
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} >srom0_seg :srom0_phdr
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.srom.rodata : ALIGN(4)
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{
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_srom_rodata_start = ABSOLUTE(.);
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*(.srom.rodata)
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_srom_rodata_end = ABSOLUTE(.);
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} >srom1_seg :srom1_phdr
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.srom.text : ALIGN(4)
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{
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_srom_text_start = ABSOLUTE(.);
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*(.srom.literal .srom.text)
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_srom_text_end = ABSOLUTE(.);
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_memmap_seg_srom1_end = ALIGN(0x8);
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_image_rom_end = ABSOLUTE(.);
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} >srom1_seg :srom1_phdr
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.WindowVectors.text : ALIGN(4)
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{
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_WindowVectors_text_start = ABSOLUTE(.);
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KEEP (*(.WindowVectors.text))
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_WindowVectors_text_end = ABSOLUTE(.);
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_memmap_seg_sram0_end = ALIGN(0x8);
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} >sram0_seg :sram0_phdr
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.DebugExceptionVector.literal : ALIGN(4)
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{
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_DebugExceptionVector_literal_start = ABSOLUTE(.);
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*(.DebugExceptionVector.literal)
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_DebugExceptionVector_literal_end = ABSOLUTE(.);
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_memmap_seg_sram1_end = ALIGN(0x8);
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} >sram1_seg :sram1_phdr
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.DebugExceptionVector.text : ALIGN(4)
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{
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_DebugExceptionVector_text_start = ABSOLUTE(.);
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KEEP (*(.DebugExceptionVector.text))
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_DebugExceptionVector_text_end = ABSOLUTE(.);
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_memmap_seg_sram2_end = ALIGN(0x8);
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} >sram2_seg :sram2_phdr
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.KernelExceptionVector.literal : ALIGN(4)
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{
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_KernelExceptionVector_literal_start = ABSOLUTE(.);
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*(.KernelExceptionVector.literal)
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_KernelExceptionVector_literal_end = ABSOLUTE(.);
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_memmap_seg_sram3_end = ALIGN(0x8);
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} >sram3_seg :sram3_phdr
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.KernelExceptionVector.text : ALIGN(4)
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{
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_KernelExceptionVector_text_start = ABSOLUTE(.);
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KEEP (*(.KernelExceptionVector.text))
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_KernelExceptionVector_text_end = ABSOLUTE(.);
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_memmap_seg_sram4_end = ALIGN(0x8);
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} >sram4_seg :sram4_phdr
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.UserExceptionVector.literal : ALIGN(4)
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{
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_UserExceptionVector_literal_start = ABSOLUTE(.);
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*(.UserExceptionVector.literal)
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_UserExceptionVector_literal_end = ABSOLUTE(.);
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_memmap_seg_sram5_end = ALIGN(0x8);
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} >sram5_seg :sram5_phdr
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.UserExceptionVector.text : ALIGN(4)
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{
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_UserExceptionVector_text_start = ABSOLUTE(.);
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KEEP (*(.UserExceptionVector.text))
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_UserExceptionVector_text_end = ABSOLUTE(.);
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_memmap_seg_sram6_end = ALIGN(0x8);
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} >sram6_seg :sram6_phdr
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.DoubleExceptionVector.literal : ALIGN(4)
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{
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_DoubleExceptionVector_literal_start = ABSOLUTE(.);
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*(.DoubleExceptionVector.literal)
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_DoubleExceptionVector_literal_end = ABSOLUTE(.);
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_memmap_seg_sram7_end = ALIGN(0x8);
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} >sram7_seg :sram7_phdr
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.DoubleExceptionVector.text : ALIGN(4)
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{
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_DoubleExceptionVector_text_start = ABSOLUTE(.);
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KEEP (*(.DoubleExceptionVector.text))
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_DoubleExceptionVector_text_end = ABSOLUTE(.);
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_memmap_seg_sram8_end = ALIGN(0x8);
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} >sram8_seg :sram8_phdr
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.sram.rodata : ALIGN(4)
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{
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_image_ram_start = ABSOLUTE(.);
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_sram_rodata_start = ABSOLUTE(.);
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*(.sram.rodata)
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_sram_rodata_end = ABSOLUTE(.);
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} >sram9_seg :sram9_phdr
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#include <linker/common-rom.ld>
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.rodata : ALIGN(4)
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{
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_rodata_start = ABSOLUTE(.);
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*(.rodata)
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*(.rodata.*)
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*(.gnu.linkonce.r.*)
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*(.rodata1)
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__XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
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KEEP (*(.xt_except_table))
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KEEP (*(.gcc_except_table))
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*(.gnu.linkonce.e.*)
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*(.gnu.version_r)
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KEEP (*(.eh_frame))
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/* C++ constructor and destructor tables, properly ordered: */
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KEEP (*crtbegin.o(.ctors))
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KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
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KEEP (*(SORT(.ctors.*)))
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KEEP (*(.ctors))
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KEEP (*crtbegin.o(.dtors))
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KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
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KEEP (*(SORT(.dtors.*)))
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KEEP (*(.dtors))
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/* C++ exception handlers table: */
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__XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
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*(.xt_except_desc)
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*(.gnu.linkonce.h.*)
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__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
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*(.xt_except_desc_end)
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*(.dynamic)
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*(.gnu.version_d)
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. = ALIGN(4); /* this table MUST be 4-byte aligned */
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_bss_table_start = ABSOLUTE(.);
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LONG(_bss_start)
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LONG(_bss_end)
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_bss_table_end = ABSOLUTE(.);
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_rodata_end = ABSOLUTE(.);
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} >sram9_seg :sram9_phdr
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.sram.text : ALIGN(4)
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{
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_sram_text_start = ABSOLUTE(.);
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*(.sram.literal .sram.text)
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_sram_text_end = ABSOLUTE(.);
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} >sram9_seg :sram9_phdr
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_image_text_start = ALIGN(4);
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.text : ALIGN(4)
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{
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_stext = .;
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_text_start = ABSOLUTE(.);
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*(.entry.text)
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*(.init.literal)
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KEEP(*(.init))
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*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
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*(.fini.literal)
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KEEP(*(.fini))
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*(.gnu.version)
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_text_end = ABSOLUTE(.);
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_etext = .;
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} >sram9_seg :sram9_phdr
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_image_text_end = .;
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.sram.data : ALIGN(4)
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{
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_sram_data_start = ABSOLUTE(.);
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*(.sram.data)
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_sram_data_end = ABSOLUTE(.);
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} >sram9_seg :sram9_phdr
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.noinit : ALIGN(4)
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{
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*(.noinit)
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*(.noinit.*)
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} >sram9_seg :sram9_phdr
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.data : ALIGN(4)
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{
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_data_start = ABSOLUTE(.);
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*(.data)
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*(.data.*)
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KEEP(*(SW_ISR_TABLE))
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*(.gnu.linkonce.d.*)
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KEEP(*(.gnu.linkonce.d.*personality*))
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*(.data1)
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*(.sdata)
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*(.sdata.*)
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*(.gnu.linkonce.s.*)
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*(.sdata2)
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*(.sdata2.*)
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*(.gnu.linkonce.s2.*)
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KEEP(*(.jcr))
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_data_end = ABSOLUTE(.);
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} >sram9_seg :sram9_phdr
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#include <linker/common-ram.ld>
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.bss (NOLOAD) : ALIGN(8)
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{
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. = ALIGN (8);
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_bss_start = ABSOLUTE(.);
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*(.dynsbss)
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*(.sbss)
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*(.sbss.*)
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*(.gnu.linkonce.sb.*)
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*(.scommon)
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*(.sbss2)
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*(.sbss2.*)
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*(.gnu.linkonce.sb2.*)
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*(.dynbss)
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*(.bss)
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*(.bss.*)
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*(.gnu.linkonce.b.*)
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*(COMMON)
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*(.sram.bss)
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. = ALIGN (8);
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_bss_end = ABSOLUTE(.);
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_end = ALIGN(0x8);
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_image_ram_end = ABSOLUTE(.);
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PROVIDE(end = ALIGN(0x8));
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_stack_sentry = ALIGN(0x8);
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_memmap_seg_sram9_end = ALIGN(0x8);
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} >sram9_seg :sram9_bss_phdr
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__stack = 0x64000000;
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_heap_sentry = 0x64000000;
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.debug 0 : { *(.debug) }
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.line 0 : { *(.line) }
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.debug_srcinfo 0 : { *(.debug_srcinfo) }
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.debug_sfnames 0 : { *(.debug_sfnames) }
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.debug_aranges 0 : { *(.debug_aranges) }
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.debug_pubnames 0 : { *(.debug_pubnames) }
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.debug_info 0 : { *(.debug_info) }
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.debug_abbrev 0 : { *(.debug_abbrev) }
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.debug_line 0 : { *(.debug_line) }
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.debug_frame 0 : { *(.debug_frame) }
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.debug_str 0 : { *(.debug_str) }
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.debug_loc 0 : { *(.debug_loc) }
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.debug_macinfo 0 : { *(.debug_macinfo) }
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.debug_weaknames 0 : { *(.debug_weaknames) }
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.debug_funcnames 0 : { *(.debug_funcnames) }
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.debug_typenames 0 : { *(.debug_typenames) }
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.debug_varnames 0 : { *(.debug_varnames) }
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.xt.insn 0 :
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{
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KEEP (*(.xt.insn))
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KEEP (*(.gnu.linkonce.x.*))
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}
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.xt.prop 0 :
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{
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KEEP (*(.xt.prop))
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KEEP (*(.xt.prop.*))
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KEEP (*(.gnu.linkonce.prop.*))
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}
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.xt.lit 0 :
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{
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KEEP (*(.xt.lit))
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KEEP (*(.xt.lit.*))
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KEEP (*(.gnu.linkonce.p.*))
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}
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.debug.xt.callgraph 0 :
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{
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KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
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}
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#ifdef CONFIG_GEN_ISR_TABLES
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#include <linker/intlist.ld>
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#endif
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}
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