64 lines
1.9 KiB
C
64 lines
1.9 KiB
C
/* pinmux_quark_mcu.h - pinmux operation for generic Quark MCU boards */
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/*
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* Copyright (c) 2016 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define PINMUX_PULLUP_OFFSET 0x00
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#define PINMUX_SLEW_OFFSET 0x10
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#define PINMUX_INPUT_OFFSET 0x20
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#define PINMUX_SELECT_OFFSET 0x30
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#define PINMUX_SELECT_REGISTER(base, reg_offset) \
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(base + PINMUX_SELECT_OFFSET + (reg_offset << 2))
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/*
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* A little decyphering of what is going on here:
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*
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* Each pinmux register rperesents a bank of 16 pins, 2 bits per pin for a total
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* of four possible settings per pin.
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*
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* The first argument to the macro is name of the u32_t's that is being used
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* to contain the bit patterns for all the configuration registers. The pin
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* number divided by 16 selects the correct register bank based on the pin
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* number.
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*
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* The pin number % 16 * 2 selects the position within the register bank for the
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* bits controlling the pin.
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*
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* All but the lower two bits of the config values are masked off to ensure
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* that we don't inadvertently affect other pins in the register bank.
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*/
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#define PIN_CONFIG(A, _pin, _func) \
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(A[((_pin) / 16)] |= ((0x3 & (_func)) << (((_pin) % 16) * 2)))
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static inline int _quark_mcu_set_mux(u32_t base, u32_t pin, u8_t func)
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{
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/*
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* the registers are 32-bit wide, but each pin requires 1 bit
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* to set the input enable bit.
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*/
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u32_t register_offset = (pin / 32) * 4;
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/*
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* Now figure out what is the full address for the register
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* we are looking for. Add the base register to the register_mask
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*/
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volatile u32_t *mux_register = (u32_t *)(base + register_offset);
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/*
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* Finally grab the pin offset within the register
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*/
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u32_t pin_offset = pin % 32;
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/*
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* MAGIC NUMBER: 0x1 is used as the pullup is a single bit in a
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* 32-bit register.
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*/
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(*(mux_register)) = ((*(mux_register)) & ~(0x1 << pin_offset)) |
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((func & 0x01) << pin_offset);
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return 0;
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}
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