142 lines
3.9 KiB
C
142 lines
3.9 KiB
C
/*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Basic initialization for the CC2650 System on Chip.
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*/
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#include <toolchain/gcc.h>
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#include <init.h>
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#include <sys_io.h>
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#include "soc.h"
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#define CCFG_SIZE 88
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/* The bootloader of the SoC (in ROM) reads configuration
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* data (CCFG) at a fixed address (last page of flash).
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* The most notable information being whether to run the
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* code stored in flash or not.
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*
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* We put configuration data in a specific section so that
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* the linker script can map it accordingly.
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*/
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const u32_t
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__ti_ccfg_section
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ti_ccfg[CCFG_SIZE / sizeof(u32_t)] = {
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0x00008001, /* EXT_LF_CLK: default values */
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0xFF13FFFF, /* MODE_CONF_1: default values */
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0x0058FFFF, /* SIZE_AND_DIS_FLAGS: 88 bytes long, no external osc. */
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0xFFFFFFFF, /* MODE_CONF: default values */
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0xFFFFFFFF, /* VOLT_LOAD_0: default values */
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0xFFFFFFFF, /* VOLT_LOAD_1: default values */
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0xFFFFFFFF, /* RTC_OFFSET: default values */
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0xFFFFFFFF, /* FREQ_OFFSET: default values */
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0xFFFFFFFF, /* IEEE_MAC_0: use MAC address from FCFG */
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0xFFFFFFFF, /* IEEE_MAC_1: use MAC address from FCFG */
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0xFFFFFFFF, /* IEEE_BLE_0: use BLE address from FCFG */
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0xFFFFFFFF, /* IEEE_BLE_1: use BLE address from FCFG */
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/* BL_CONFIG: disable backdoor and bootloader,
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* default pin, default active level (high)
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*/
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CC2650_CCFG_BACKDOOR_DISABLED |
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(0xFF << CC2650_CCFG_BL_CONFIG_BL_PIN_NUMBER_POS) |
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(0x1 << CC2650_CCFG_BL_CONFIG_BL_LEVEL_POS) |
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0x00FE0000 | /* reserved */
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CC2650_CCFG_BOOTLOADER_DISABLED,
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0xFFFFFFFF, /* ERASE_CONF: default values (banks + chip erase) */
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/* CCFG_TI_OPTIONS: disable TI failure analysis */
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CC2650_CCFG_TI_FA_DISABLED |
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0xFFFFFF00, /* reserved */
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0xFFC5C5C5, /* CCFG_TAP_DAP_0: default values */
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0xFFC5C5C5, /* CCFG_TAP_DAP_1: default values */
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/* IMAGE_VALID_CONF: authorize program on flash to run */
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CC2650_CCFG_IMAGE_IS_VALID,
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/* Make all flash chip programmable + erasable
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* (which is default)
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*/
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0xFFFFFFFF, /* CCFG_PROT_31_0 */
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0xFFFFFFFF, /* CCFG_PROT_61_32 */
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0xFFFFFFFF, /* CCFG_PROT_95_64 */
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0xFFFFFFFF /* CCFG_PROT_127_96 */
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};
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/* PRCM Registers */
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static const u32_t clkloadctl =
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REG_ADDR(TI_CC2650_PRCM_40082000_BASE_ADDRESS,
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CC2650_PRCM_CLKLOADCTL);
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static const u32_t gpioclkgr =
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REG_ADDR(TI_CC2650_PRCM_40082000_BASE_ADDRESS,
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CC2650_PRCM_GPIOCLKGR);
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static const u32_t pdctl0 =
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REG_ADDR(TI_CC2650_PRCM_40082000_BASE_ADDRESS,
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CC2650_PRCM_PDCTL0);
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static const u32_t pdstat0 =
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REG_ADDR(TI_CC2650_PRCM_40082000_BASE_ADDRESS,
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CC2650_PRCM_PDSTAT0);
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#ifdef CONFIG_SERIAL
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static const u32_t uartclkgr =
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REG_ADDR(TI_CC2650_PRCM_40082000_BASE_ADDRESS,
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CC2650_PRCM_UARTCLKGR);
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#endif
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/* Setup power and clock for needed hardware modules. */
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static void setup_modules_prcm(void)
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{
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#if defined(CONFIG_GPIO_CC2650) || \
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defined(CONFIG_SERIAL)
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/* Setup power */
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#if defined(CONFIG_GPIO_CC2650)
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sys_set_bit(pdctl0, CC2650_PRCM_PDCTL0_PERIPH_ON_POS);
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#endif
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#ifdef CONFIG_SERIAL
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sys_set_bit(pdctl0, CC2650_PRCM_PDCTL0_SERIAL_ON_POS);
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#endif
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/* Setup clocking */
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#ifdef CONFIG_GPIO_CC2650
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sys_set_bit(gpioclkgr, CC2650_PRCM_GPIOCLKGR_CLK_EN_POS);
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#endif
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#ifdef CONFIG_SERIAL
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sys_set_bit(uartclkgr, CC2650_PRCM_UARTCLKGR_CLK_EN_POS);
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#endif
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/* Reload clocking configuration for device */
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sys_set_bit(clkloadctl, CC2650_PRCM_CLKLOADCTL_LOAD_POS);
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/* Wait for power to be completely on, to avoid bus faults
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* when accessing modules' registers.
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*/
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#if defined(CONFIG_GPIO_CC2650)
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while (!(sys_read32(pdstat0) &
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BIT(CC2650_PRCM_PDSTAT0_PERIPH_ON_POS))) {
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continue;
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}
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#endif
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#if defined(CONFIG_SERIAL)
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while (!(sys_read32(pdstat0) &
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BIT(CC2650_PRCM_PDSTAT0_SERIAL_ON_POS))) {
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continue;
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}
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#endif
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#endif
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}
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static int ti_cc2650(struct device *dev)
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{
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ARG_UNUSED(dev);
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NMI_INIT();
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setup_modules_prcm();
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return 0;
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}
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SYS_INIT(ti_cc2650, PRE_KERNEL_1, 0);
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int bit_is_set(u32_t reg, u8_t bit)
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{
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return sys_read32(reg) & BIT(bit);
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}
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