133 lines
3.1 KiB
C
133 lines
3.1 KiB
C
/*
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* Copyright (c) 2017, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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#include <device.h>
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#include <init.h>
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#include <soc.h>
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#include <uart.h>
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#include <linker/sections.h>
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#include <fsl_common.h>
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#include <fsl_clock.h>
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#include <arch/cpu.h>
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#define ER32KSEL_OSC32KCLK (0)
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#define ER32KSEL_RTC (2)
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#define ER32KSEL_LPO1KHZ (3)
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#define LPUART0SRC_OSCERCLK (1)
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#define CLKDIV1_DIVBY2 (1)
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/*
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* KW41Z Flash configuration fields
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* These 16 bytes, which must be loaded to address 0x400, include default
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* protection and security settings.
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* They are loaded at reset to various Flash Memory module (FTFE) registers.
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*
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* The structure is:
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* -Backdoor Comparison Key for unsecuring the MCU - 8 bytes
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* -Program flash protection bytes, 4 bytes, written to FPROT0-3
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* -Flash security byte, 1 byte, written to FSEC
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* -Flash nonvolatile option byte, 1 byte, written to FOPT
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* -Reserved, 1 byte, (Data flash protection byte for FlexNVM)
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* -Reserved, 1 byte, (EEPROM protection byte for FlexNVM)
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*
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*/
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u8_t __kinetis_flash_config_section __kinetis_flash_config[] = {
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/* Backdoor Comparison Key (unused) */
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0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
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/* Program flash protection; 1 bit/region - 0=protected, 1=unprotected
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*/
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0xFF, 0xFF, 0xFF, 0xFF,
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/*
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* Flash security: Backdoor key disabled, Mass erase enabled,
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* Factory access enabled, MCU is unsecure
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*/
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0xFE,
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/* Flash nonvolatile option: NMI enabled, EzPort enabled, Normal boot */
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0xFF,
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/* Reserved for FlexNVM feature (unsupported by this MCU) */
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0xFF, 0xFF};
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static const osc_config_t oscConfig = {
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.freq = CONFIG_OSC_XTAL0_FREQ,
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#if defined(CONFIG_OSC_EXTERNAL)
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.workMode = kOSC_ModeExt,
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#elif defined(CONFIG_OSC_LOW_POWER)
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.workMode = kOSC_ModeOscLowPower,
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#elif defined(CONFIG_OSC_HIGH_GAIN)
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.workMode = kOSC_ModeOscHighGain,
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#else
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#error "An oscillator mode must be defined"
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#endif
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};
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static const sim_clock_config_t simConfig = {
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.er32kSrc = ER32KSEL_OSC32KCLK,
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.clkdiv1 = SIM_CLKDIV1_OUTDIV4(CLKDIV1_DIVBY2),
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};
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/* This function comes from the MCUX SDK:
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* ext/hal/nxp/mcux/devices/MKW41Z4/clock_config.c
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*/
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static void CLOCK_SYS_FllStableDelay(void)
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{
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u32_t i = 30000U;
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while (i--) {
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__NOP();
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}
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}
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static ALWAYS_INLINE void clkInit(void)
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{
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CLOCK_SetSimSafeDivs();
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CLOCK_InitOsc0(&oscConfig);
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CLOCK_SetXtal0Freq(CONFIG_OSC_XTAL0_FREQ);
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CLOCK_BootToFeeMode(kMCG_OscselOsc, CONFIG_MCG_FRDIV, kMCG_Dmx32Default,
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kMCG_DrsMid, CLOCK_SYS_FllStableDelay);
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CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow,
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CONFIG_MCG_FCRDIV);
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CLOCK_SetSimConfig(&simConfig);
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#if CONFIG_UART_MCUX_LPUART_0
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CLOCK_SetLpuartClock(LPUART0SRC_OSCERCLK);
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#endif
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}
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static int kwx_init(struct device *arg)
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{
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ARG_UNUSED(arg);
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unsigned int oldLevel; /* old interrupt lock level */
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/* disable interrupts */
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oldLevel = irq_lock();
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/* Disable the watchdog */
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SIM->COPC = 0;
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/* Initialize system clock to 40 MHz */
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clkInit();
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/*
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* install default handler that simply resets the CPU
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* if configured in the kernel, NOP otherwise
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*/
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NMI_INIT();
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/* restore interrupt state */
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irq_unlock(oldLevel);
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return 0;
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}
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SYS_INIT(kwx_init, PRE_KERNEL_1, 0);
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