134 lines
3.5 KiB
C
134 lines
3.5 KiB
C
/*
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* Copyright (c) 2017, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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#include <device.h>
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#include <init.h>
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#include <soc.h>
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#include <linker/sections.h>
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#include <fsl_common.h>
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#include <fsl_clock.h>
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#include <arch/cpu.h>
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#define LPSCI0SRC_MCGFLLCLK (1)
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*
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* KL25Z Flash configuration fields
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* These 16 bytes, which must be loaded to address 0x400, include default
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* protection and security settings.
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* They are loaded at reset to various Flash Memory module (FTFE) registers.
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*
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* The structure is:
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* -Backdoor Comparison Key for unsecuring the MCU - 8 bytes
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* -Program flash protection bytes, 4 bytes, written to FPROT0-3
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* -Flash security byte, 1 byte, written to FSEC
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* -Flash nonvolatile option byte, 1 byte, written to FOPT
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* -Reserved, 1 byte, (Data flash protection byte for FlexNVM)
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* -Reserved, 1 byte, (EEPROM protection byte for FlexNVM)
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*
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*/
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u8_t __kinetis_flash_config_section __kinetis_flash_config[] = {
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/* Backdoor Comparison Key (unused) */
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0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
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/* Program flash protection; 1 bit/region - 0=protected, 1=unprotected
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*/
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0xFF, 0xFF, 0xFF, 0xFF,
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/*
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* Flash security: Backdoor key disabled, Mass erase enabled,
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* Factory access enabled, MCU is unsecure
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*/
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0xFE,
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/* Flash nonvolatile option: NMI enabled, EzPort enabled, Normal boot */
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0xFF,
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/* Reserved for FlexNVM feature (unsupported by this MCU) */
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0xFF, 0xFF};
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static ALWAYS_INLINE void clkInit(void)
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{
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/*
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* Core clock: 48MHz
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* Bus clock: 24MHz
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*/
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const mcg_pll_config_t pll0Config = {
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.enableMode = 0U, .prdiv = CONFIG_MCG_PRDIV0, .vdiv = CONFIG_MCG_VDIV0,
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};
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const sim_clock_config_t simConfig = {
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.pllFllSel = 1U, /* PLLFLLSEL select PLL. */
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.er32kSrc = 3U, /* ERCLK32K selection, use LPO. */
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.clkdiv1 = 0x10010000U, /* SIM_CLKDIV1. */
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};
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const osc_config_t oscConfig = {.freq = CONFIG_OSC_XTAL0_FREQ,
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.capLoad = 0,
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#if defined(CONFIG_OSC_EXTERNAL)
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.workMode = kOSC_ModeExt,
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#elif defined(CONFIG_OSC_LOW_POWER)
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.workMode = kOSC_ModeOscLowPower,
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#elif defined(CONFIG_OSC_HIGH_GAIN)
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.workMode = kOSC_ModeOscHighGain,
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#else
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#error "An oscillator mode must be defined"
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#endif
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.oscerConfig = {
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.enableMode = kOSC_ErClkEnable,
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#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && \
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FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
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.erclkDiv = 0U,
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#endif
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} };
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CLOCK_SetSimSafeDivs();
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CLOCK_InitOsc0(&oscConfig);
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/* Passing the XTAL0 frequency to clock driver. */
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CLOCK_SetXtal0Freq(CONFIG_OSC_XTAL0_FREQ);
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CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &pll0Config);
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CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow, 0);
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CLOCK_SetSimConfig(&simConfig);
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#ifdef CONFIG_UART_MCUX_LPSCI_0
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CLOCK_SetLpsci0Clock(LPSCI0SRC_MCGFLLCLK);
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#endif
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#if CONFIG_USB_KINETIS
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CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcPll0,
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
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#endif
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}
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static int kl2x_init(struct device *arg)
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{
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ARG_UNUSED(arg);
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unsigned int oldLevel; /* old interrupt lock level */
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/* disable interrupts */
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oldLevel = irq_lock();
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/* Disable the watchdog */
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SIM->COPC = 0;
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/* Initialize system clock to 48 MHz */
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clkInit();
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/*
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* install default handler that simply resets the CPU
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* if configured in the kernel, NOP otherwise
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*/
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NMI_INIT();
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/* restore interrupt state */
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irq_unlock(oldLevel);
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return 0;
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}
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SYS_INIT(kl2x_init, PRE_KERNEL_1, 0);
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