147 lines
3.8 KiB
C
147 lines
3.8 KiB
C
/*
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* Copyright (c) 2017 Nordic Semiconductor ASA
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* Copyright (c) 2023 Arm Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief CMSIS interface file
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*
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* This header populates the default values required to configure the
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* ARM CMSIS Core headers.
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*/
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#ifndef ZEPHYR_MODULES_CMSIS_CMSIS_M_DEFAULTS_H_
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#define ZEPHYR_MODULES_CMSIS_CMSIS_M_DEFAULTS_H_
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#include <zephyr/arch/arm/cortex_m/nvic.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Fill in CMSIS required values for non-CMSIS compliant SoCs.
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* Use __NVIC_PRIO_BITS as it is required and simple to check, but
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* ultimately all SoCs will define their own CMSIS types and constants.
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*/
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#ifndef __NVIC_PRIO_BITS
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typedef enum {
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Reset_IRQn = -15,
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NonMaskableInt_IRQn = -14,
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HardFault_IRQn = -13,
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#if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
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MemoryManagement_IRQn = -12,
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BusFault_IRQn = -11,
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UsageFault_IRQn = -10,
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#if defined(CONFIG_ARM_SECURE_FIRMWARE)
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SecureFault_IRQn = -9,
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#endif /* CONFIG_ARM_SECURE_FIRMWARE */
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#endif /* CONFIG_ARMV7_M_ARMV8_M_MAINLINE */
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SVCall_IRQn = -5,
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DebugMonitor_IRQn = -4,
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PendSV_IRQn = -2,
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SysTick_IRQn = -1,
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Max_IRQn = CONFIG_NUM_IRQS,
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} IRQn_Type;
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#if defined(CONFIG_CPU_CORTEX_M0)
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#define __CM0_REV 0
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#elif defined(CONFIG_CPU_CORTEX_M0PLUS)
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#define __CM0PLUS_REV 0
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#elif defined(CONFIG_CPU_CORTEX_M1)
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#define __CM1_REV 0
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#elif defined(CONFIG_CPU_CORTEX_M3)
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#define __CM3_REV 0
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#elif defined(CONFIG_CPU_CORTEX_M4)
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#define __CM4_REV 0
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#elif defined(CONFIG_CPU_CORTEX_M7)
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#define __CM7_REV 0
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#elif defined(CONFIG_CPU_CORTEX_M23)
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#define __CM23_REV 0
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#elif defined(CONFIG_CPU_CORTEX_M33)
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#define __CM33_REV 0
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#elif defined(CONFIG_CPU_CORTEX_M55)
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#define __CM55_REV 0
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#elif defined(CONFIG_CPU_CORTEX_M85)
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#define __CM85_REV 0
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#else
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#error "Unknown Cortex-M device"
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#endif
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#define __NVIC_PRIO_BITS NUM_IRQ_PRIO_BITS
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#define __Vendor_SysTickConfig 0 /* Default to standard SysTick */
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#endif /* __NVIC_PRIO_BITS */
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#ifndef __MPU_PRESENT
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#define __MPU_PRESENT CONFIG_CPU_HAS_ARM_MPU
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#endif
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#ifndef __FPU_PRESENT
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#define __FPU_PRESENT CONFIG_CPU_HAS_FPU
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#endif
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#ifndef __FPU_DP
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#define __FPU_DP CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION
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#endif
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#ifndef __VTOR_PRESENT
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#define __VTOR_PRESENT CONFIG_CPU_CORTEX_M_HAS_VTOR
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#endif
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#ifndef __DSP_PRESENT
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#define __DSP_PRESENT CONFIG_ARMV8_M_DSP
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#endif
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#ifndef __ICACHE_PRESENT
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#define __ICACHE_PRESENT CONFIG_CPU_HAS_ICACHE
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#endif
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#ifndef __DCACHE_PRESENT
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#define __DCACHE_PRESENT CONFIG_CPU_HAS_DCACHE
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#endif
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#ifndef __MVE_PRESENT
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#define __MVE_PRESENT CONFIG_ARMV8_1_M_MVEI
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#endif
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#ifndef __SAUREGION_PRESENT
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#define __SAUREGION_PRESENT CONFIG_CPU_HAS_ARM_SAU
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#endif
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#ifndef __PMU_PRESENT
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#define __PMU_PRESENT CONFIG_ARMV8_1_M_PMU
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#define __PMU_NUM_EVENTCNT CONFIG_ARMV8_1_M_PMU_EVENTCNT
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#endif
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#ifdef __cplusplus
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}
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#endif
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#if defined(CONFIG_CPU_CORTEX_M0)
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#include <core_cm0.h>
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#elif defined(CONFIG_CPU_CORTEX_M0PLUS)
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#include <core_cm0plus.h>
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#elif defined(CONFIG_CPU_CORTEX_M1)
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#include <core_cm1.h>
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#elif defined(CONFIG_CPU_CORTEX_M3)
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#include <core_cm3.h>
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#elif defined(CONFIG_CPU_CORTEX_M4)
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#include <core_cm4.h>
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#elif defined(CONFIG_CPU_CORTEX_M7)
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#include <core_cm7.h>
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#elif defined(CONFIG_CPU_CORTEX_M23)
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#include <core_cm23.h>
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#elif defined(CONFIG_CPU_CORTEX_M33)
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#include <core_cm33.h>
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#elif defined(CONFIG_CPU_CORTEX_M55)
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#include <core_cm55.h>
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#elif defined(CONFIG_CPU_CORTEX_M85)
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#include <core_cm85.h>
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#else
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#error "Unknown Cortex-M device"
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#endif
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#endif /* ZEPHYR_MODULES_CMSIS_CMSIS_M_DEFAULTS_H_ */
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