168 lines
4.1 KiB
C
168 lines
4.1 KiB
C
/* SPDX-License-Identifier: Apache-2.0 */
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/*
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* Copyright (c) 2023 Intel Corporation
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*
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* Author: Adrian Warecki <adrian.warecki@intel.com>
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*/
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#ifndef ZEPHYR_DRIVERS_WATCHDOG_WDT_INTEL_ADSP_H_
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#define ZEPHYR_DRIVERS_WATCHDOG_WDT_INTEL_ADSP_H_
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/*
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* Get register offset for core
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*/
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#define DSPBRx_OFFSET(x) (0x0020 * (x))
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/*
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* DSPCxWDTCS
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* DSP Core Watch Dog Timer Control & Status
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*
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* Offset: 04h
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* Block: DSPBRx
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*
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* This register controls the DSP Core watch dog timer policy.
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*/
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#define DSPCxWDTCS 0x0004
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/*
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* Pause Code
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* type: WO, rst: 00b, rst domain: nan
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*
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* FW write 76h as the code to set the PAUSED bit. Other value are ignored and has no effect.
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*/
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#define DSPCxWDTCS_PCODE GENMASK(7, 0)
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#define DSPCxWDTCS_PCODE_VALUE 0x76
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/*
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* Paused
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* type: RW/1C, rst: 0b, rst domain: DSPLRST
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*
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* When set, it pauses the watch dog timer. Set when 76h is written to the PCODE
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* field. Clear when FW writes a 1 to the bit.
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*/
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#define DSPCxWDTCS_PAUSED BIT(8)
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/*
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* Second Time Out Reset Enable
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* type: RW/1S, rst: 0b, rst domain: DSPLRST
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*
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* When set, it allow the DSP Core reset to take place upon second time out of the
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* watch dog timer. Clear when DSPCCTL.CPA = 0. Set when FW writes a 1 to the bit.
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*/
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#define DSPCxWDTCS_STORE BIT(9)
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/*
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* DSPCxWDTIPPTR
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* DSP Core Watch Dog Timer IP Pointer
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*
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* Offset: 08h
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* Block: DSPBRx
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*
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* This register provides the pointer to the DSP Core watch dog timer IP registers.
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*/
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#define DSPCxWDTIPPTR 0x0008
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/*
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* IP Pointer
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* type: RO, rst: 07 8300h + 100h * x, rst domain: nan
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*
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* This field contains the offset to the IP.
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*/
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#define DSPCxWDTIPPTR_PTR GENMASK(20, 0)
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/*
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* IP Version
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* type: RO, rst: 000b, rst domain: nan
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*
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* This field indicates the version of the IP.
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*/
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#define DSPCxWDTIPPTR_VER GENMASK(23, 21)
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/**
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* @brief Set pause signal
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*
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* Sets the pause signal to stop the watchdog timing
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*
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* @param base Device base address.
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* @param core Core ID
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*/
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static inline void intel_adsp_wdt_pause(uint32_t base, const uint32_t core)
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{
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const uint32_t reg_addr = base + DSPCxWDTCS + DSPBRx_OFFSET(core);
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uint32_t control;
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control = sys_read32(reg_addr);
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control &= DSPCxWDTCS_STORE;
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control |= FIELD_PREP(DSPCxWDTCS_PCODE, DSPCxWDTCS_PCODE_VALUE);
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sys_write32(control, reg_addr);
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}
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/**
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* @brief Clear pause signal
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*
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* Clears the pause signal to resume the watchdog timing
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*
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* @param base Device base address.
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* @param core Core ID
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*/
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static inline void intel_adsp_wdt_resume(uint32_t base, const uint32_t core)
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{
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const uint32_t reg_addr = base + DSPCxWDTCS + DSPBRx_OFFSET(core);
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uint32_t control;
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control = sys_read32(reg_addr);
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control &= DSPCxWDTCS_STORE;
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control |= DSPCxWDTCS_PAUSED;
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sys_write32(control, reg_addr);
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}
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/**
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* @brief Second Time Out Reset Enable
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*
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* When set, it allow the DSP Core reset to take place upon second time out of the watchdog timer.
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*
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* @param base Device base address.
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* @param core Core ID
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*/
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static inline void intel_adsp_wdt_reset_set(uint32_t base, const uint32_t core, const bool enable)
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{
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sys_write32(enable ? DSPCxWDTCS_STORE : 0, base + DSPCxWDTCS + DSPBRx_OFFSET(core));
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}
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/*
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* Second Time Out Reset Enable
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* type: RW/1S, rst: 0b, rst domain: DSPLRST
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*
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* When set, it allow the DSP Core reset to take place upon second time out of the
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* watch dog timer. Clear when DSPCCTL.CPA = 0. Set when FW writes a 1 to the bit.
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*/
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#define DSPCxWDTCS_STORE BIT(9)
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/**
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* @brief Get watchdog IP pointer for specified core.
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*
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* Returns the base address of the watchdog IP
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*
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* @param base Device base address.
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* @param core Core ID
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*/
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static inline uint32_t intel_adsp_wdt_pointer_get(uint32_t base, const uint32_t core)
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{
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return FIELD_GET(DSPCxWDTIPPTR_PTR, sys_read32(base + DSPCxWDTIPPTR + DSPBRx_OFFSET(core)));
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}
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/**
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* @brief Get watchdog version
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*
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* Returns the version of the watchdog IP
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*
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* @param base Device base address.
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* @param core Core ID
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*/
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static inline uint32_t intel_adsp_wdt_version_get(uint32_t base, const uint32_t core)
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{
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return FIELD_GET(DSPCxWDTIPPTR_VER, sys_read32(base + DSPCxWDTIPPTR + DSPBRx_OFFSET(core)));
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}
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#endif /* ZEPHYR_DRIVERS_WATCHDOG_WDT_INTEL_ADSP_H_ */
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