302 lines
8.1 KiB
C
302 lines
8.1 KiB
C
/*
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* Copyright (C) 2023 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT cdns_sdhc
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#include <zephyr/drivers/sdhc.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/reset.h>
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#include "sdhc_cdns_ll.h"
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#define SDHC_CDNS_DESC_SIZE (1<<20)
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#define COMBOPHY_ADDR_MASK 0x0000FFFFU
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#define DEV_CFG(_dev) ((const struct sdhc_cdns_config *)(_dev)->config)
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#define DEV_DATA(_dev) ((struct sdhc_cdns_data *const)(_dev)->data)
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LOG_MODULE_REGISTER(sdhc_cdns, CONFIG_SDHC_LOG_LEVEL);
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/* SDMMC operations FPs are the element of structure*/
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static const struct sdhc_cdns_ops *cdns_sdmmc_ops;
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struct sdhc_cdns_config {
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DEVICE_MMIO_NAMED_ROM(reg_base);
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DEVICE_MMIO_NAMED_ROM(combo_phy);
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/* Clock rate for host */
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uint32_t clk_rate;
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/* power delay prop for host */
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uint32_t power_delay_ms;
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/* run time device structure */
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const struct device *cdns_clk_dev;
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/* type to identify a clock controller sub-system */
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clock_control_subsys_t clkid;
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/* Reset controller device configuration. */
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const struct reset_dt_spec reset_sdmmc;
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const struct reset_dt_spec reset_sdmmcocp;
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const struct reset_dt_spec reset_softphy;
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};
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struct sdhc_cdns_data {
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DEVICE_MMIO_NAMED_RAM(reg_base);
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DEVICE_MMIO_NAMED_RAM(combo_phy);
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/* Host controller parameters */
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struct sdhc_cdns_params params;
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/* sdmmc device informartaion for host */
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struct sdmmc_device_info info;
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/* Input/Output configuration */
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struct sdhc_io host_io;
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};
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static int sdhc_cdns_request(const struct device *dev,
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struct sdhc_command *cmd,
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struct sdhc_data *data)
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{
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int ret = 0;
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struct sdmmc_cmd cdns_sdmmc_cmd;
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if (cmd == NULL) {
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LOG_ERR("Wrong CMD parameter");
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return -EINVAL;
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}
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/* Initialization of command structure */
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cdns_sdmmc_cmd.cmd_idx = cmd->opcode;
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cdns_sdmmc_cmd.cmd_arg = cmd->arg;
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cdns_sdmmc_cmd.resp_type = (cmd->response_type & SDHC_NATIVE_RESPONSE_MASK);
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/* Sending command as per the data or non data */
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if (data) {
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ret = cdns_sdmmc_ops->prepare(data->block_addr, (uintptr_t)data->data,
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data);
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if (ret != 0) {
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LOG_ERR("DMA Prepare failed");
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return -EINVAL;
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}
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}
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ret = cdns_sdmmc_ops->send_cmd(&cdns_sdmmc_cmd, data);
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if (ret == 0) {
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if (cmd->opcode == SD_READ_SINGLE_BLOCK || cmd->opcode == SD_APP_SEND_SCR ||
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cmd->opcode == SD_READ_MULTIPLE_BLOCK) {
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if (data == NULL) {
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LOG_ERR("Invalid data parameter");
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return -ENODATA;
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}
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ret = cdns_sdmmc_ops->cache_invd(data->block_addr, (uintptr_t)data->data,
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data->block_size);
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if (ret != 0) {
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return ret;
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}
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}
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}
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/* copying all responses as per response type */
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for (int i = 0; i < 4; i++) {
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cmd->response[i] = cdns_sdmmc_cmd.resp_data[i];
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}
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return ret;
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}
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static int sdhc_cdns_get_card_present(const struct device *dev)
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{
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return cdns_sdmmc_ops->card_present();
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}
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static int sdhc_cdns_card_busy(const struct device *dev)
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{
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return cdns_sdmmc_ops->busy();
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}
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static int sdhc_cdns_get_host_props(const struct device *dev,
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struct sdhc_host_props *props)
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{
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const struct sdhc_cdns_config *sdhc_config = DEV_CFG(dev);
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memset(props, 0, sizeof(struct sdhc_host_props));
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props->f_min = SDMMC_CLOCK_400KHZ;
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/*
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* default max speed is 25MHZ, as per SCR register
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* it will switch accordingly
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*/
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props->f_max = SD_CLOCK_25MHZ;
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props->power_delay = sdhc_config->power_delay_ms;
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props->host_caps.vol_330_support = true;
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props->is_spi = false;
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return 0;
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}
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static int sdhc_cdns_reset(const struct device *dev)
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{
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return cdns_sdmmc_ops->reset();
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}
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static int sdhc_cdns_init(const struct device *dev)
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{
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struct sdhc_cdns_data *const data = DEV_DATA(dev);
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const struct sdhc_cdns_config *sdhc_config = DEV_CFG(dev);
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int ret;
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/* SDHC reg base */
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DEVICE_MMIO_NAMED_MAP(dev, reg_base, K_MEM_CACHE_NONE);
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/* ComboPhy reg base */
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DEVICE_MMIO_NAMED_MAP(dev, combo_phy, K_MEM_CACHE_NONE);
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/* clock setting */
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if (sdhc_config->clk_rate == 0U) {
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if (!device_is_ready(sdhc_config->cdns_clk_dev)) {
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LOG_ERR("Clock controller device is not ready");
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return -EINVAL;
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}
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ret = clock_control_get_rate(sdhc_config->cdns_clk_dev,
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sdhc_config->clkid, &data->params.clk_rate);
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if (ret != 0) {
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return ret;
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}
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} else {
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data->params.clk_rate = sdhc_config->clk_rate;
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}
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/* Setting regbase */
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data->params.reg_base = DEVICE_MMIO_NAMED_GET(dev, reg_base);
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data->params.reg_phy = DEVICE_MMIO_NAMED_GET(dev, combo_phy);
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data->params.combophy = (DEVICE_MMIO_NAMED_ROM_PTR((dev),
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combo_phy)->phys_addr);
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data->params.combophy = (data->params.combophy & COMBOPHY_ADDR_MASK);
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/* resetting the lines */
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if (sdhc_config->reset_sdmmc.dev != NULL) {
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if (!device_is_ready(sdhc_config->reset_sdmmc.dev) ||
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!device_is_ready(sdhc_config->reset_sdmmcocp.dev) ||
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!device_is_ready(sdhc_config->reset_softphy.dev)) {
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LOG_ERR("Reset device not found");
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return -ENODEV;
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}
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ret = reset_line_toggle(sdhc_config->reset_softphy.dev,
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sdhc_config->reset_softphy.id);
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if (ret != 0) {
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LOG_ERR("Softphy Reset failed");
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return ret;
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}
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ret = reset_line_toggle(sdhc_config->reset_sdmmc.dev,
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sdhc_config->reset_sdmmc.id);
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if (ret != 0) {
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LOG_ERR("sdmmc Reset failed");
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return ret;
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}
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ret = reset_line_toggle(sdhc_config->reset_sdmmcocp.dev,
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sdhc_config->reset_sdmmcocp.id);
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if (ret != 0) {
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LOG_ERR("sdmmcocp Reset failed");
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return ret;
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}
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}
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/* Init function to call lower layer file */
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sdhc_cdns_sdmmc_init(&data->params, &data->info, &cdns_sdmmc_ops);
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ret = sdhc_cdns_reset(dev);
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if (ret != 0U) {
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LOG_ERR("Card reset failed");
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return ret;
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}
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/* Init operation called for register initialisation */
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ret = cdns_sdmmc_ops->init();
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if (ret != 0U) {
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LOG_ERR("Card initialization failed");
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return ret;
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}
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return 0;
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}
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static int sdhc_cdns_set_io(const struct device *dev, struct sdhc_io *ios)
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{
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struct sdhc_cdns_data *data = dev->data;
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struct sdhc_io *host_io = &data->host_io;
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if (host_io->bus_width != ios->bus_width || host_io->clock !=
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ios->clock) {
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host_io->bus_width = ios->bus_width;
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host_io->clock = ios->clock;
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return cdns_sdmmc_ops->set_ios(ios->clock, ios->bus_width);
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}
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return 0;
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}
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static const struct sdhc_driver_api sdhc_cdns_api = {
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.request = sdhc_cdns_request,
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.set_io = sdhc_cdns_set_io,
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.get_host_props = sdhc_cdns_get_host_props,
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.get_card_present = sdhc_cdns_get_card_present,
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.reset = sdhc_cdns_reset,
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.card_busy = sdhc_cdns_card_busy,
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};
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#define SDHC_CDNS_CLOCK_RATE_INIT(inst) \
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COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, clock_frequency), \
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( \
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.clk_rate = DT_INST_PROP(inst, clock_frequency), \
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.cdns_clk_dev = NULL, \
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.clkid = (clock_control_subsys_t)0, \
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), \
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( \
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.clk_rate = 0, \
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.cdns_clk_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(inst)), \
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.clkid = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(inst, clkid), \
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) \
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)
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#define SDHC_CDNS_RESET_SPEC_INIT(inst) \
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.reset_sdmmc = RESET_DT_SPEC_INST_GET_BY_IDX(inst, 0), \
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.reset_sdmmcocp = RESET_DT_SPEC_INST_GET_BY_IDX(inst, 1),\
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.reset_softphy = RESET_DT_SPEC_INST_GET_BY_IDX(inst, 2),
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#define SDHC_CDNS_INIT(inst) \
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static struct sdhc_cdns_desc cdns_desc \
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[CONFIG_CDNS_DESC_COUNT]; \
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\
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static const struct sdhc_cdns_config sdhc_cdns_config_##inst = {\
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DEVICE_MMIO_NAMED_ROM_INIT_BY_NAME( \
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reg_base, DT_DRV_INST(inst)), \
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DEVICE_MMIO_NAMED_ROM_INIT_BY_NAME( \
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combo_phy, DT_DRV_INST(inst)), \
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SDHC_CDNS_CLOCK_RATE_INIT(inst) \
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IF_ENABLED(DT_INST_NODE_HAS_PROP(inst, resets), \
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(SDHC_CDNS_RESET_SPEC_INIT(inst))) \
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.power_delay_ms = DT_INST_PROP(inst, power_delay_ms), \
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}; \
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static struct sdhc_cdns_data sdhc_cdns_data_##inst = { \
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.params = { \
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.bus_width = SDHC_BUS_WIDTH1BIT, \
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.desc_base = (uintptr_t) &cdns_desc, \
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.desc_size = SDHC_CDNS_DESC_SIZE, \
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.flags = 0, \
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}, \
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.info = { \
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.cdn_sdmmc_dev_type = SD_DS, \
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.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3, \
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}, \
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}; \
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DEVICE_DT_INST_DEFINE(inst, \
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&sdhc_cdns_init, \
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NULL, \
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&sdhc_cdns_data_##inst, \
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&sdhc_cdns_config_##inst, \
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POST_KERNEL, \
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CONFIG_SDHC_INIT_PRIORITY, \
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&sdhc_cdns_api);
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DT_INST_FOREACH_STATUS_OKAY(SDHC_CDNS_INIT)
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